Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement

• US 20080157224A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chikarmane, Vinay B., Fischer, Kevin J., Peterson, Brennan L.
• Granted Patent: US 7,719,062 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.

Claims

1. An n-type semiconductor device comprising:

an n-type transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder; and

a slot contact in contact with a portion of the contact region below the gate stack, the slot contact including an intrinsically stressed barrier plug and a contact metal;

wherein the barrier plug induces a tensile stress on the channel region.

2. The device of claim 1, wherein the volume of contact metal is greater than the volume of barrier plug.

3. The device of claim 1, wherein the contact metal comprises at least 75% of the volume of the slot contact.

4. The device of claim 1, wherein the slot contact further comprises an adhesion layer.

5. The device of claim 1, wherein the slot contact is at least twice as long as it is wide.

6. A method of forming an n-type semiconductor device comprising:

forming an n-type transistor including a gate stack and a contact region, the gate stack defining a channel region thereunder;

disposing a dielectric layer over the transistor;

forming an opening in the dielectric layer to expose the contact region, the opening extending below the gate stack;

disposing a barrier plug within a portion of the opening, the barrier plug inducing a tensile stress in the transistor channel region; and

filling the remaining of the opening with a contact metal.

7. The method of claim 6, further comprising disposing an adhesion layer in the opening prior to disposing the barrier plug.

8. The method of claim 6, wherein disposing the adhesion layer comprises disposing a Ti and TiN bi-layer.

9. The method of claim 8, wherein disposing the Ti layer includes sputtering.

10. The method of claim 8, wherein disposing the TiN layer includes chemical vapor deposition.

11. The method of claim 6, wherein disposing the barrier plug includes chemical vapor deposition.

12. The method of claim 11, wherein chemical vapor deposition includes a WF₆H precursor.

13. The method of claim 12, wherein chemical vapor deposition occurs between approximately 325 C and 425 C.

14. The method of claim 6, further comprising recess etching a portion of source and drain regions prior to forming the contact region.

15. The method of claim 14, wherein recess etching comprises isotropic wet etching.

16. The method of claim 6, wherein the barrier plug is disposed with a bottom-up fill process.

17. The method of claim 6, wherein filling the remaining of the opening with a contact metal comprises electroless growth of Cu.

18. The method of claim 6, wherein filling the remaining of the opening with a contact metal comprises electrolytic growth of Cu.

19. A method of forming an integrated semiconductor device comprising:

forming an NMOS transistor including a first gate stack and a first contact region, the first gate stack defining a first channel region thereunder;

forming a PMOS transistor including a second gate stack and a second contact region, the second gate stack defining a second channel region thereunder;

disposing a dielectric layer over the NMOS and PMOS transistors;

forming a first opening in the dielectric layer to expose the first contact region of the NMOS transistor, the opening extending below the first gate stack;

forming a second opening in the dielectric layer to expose the second contact region the PMOS transistor, wherein the second opening does not extend below the second gate stack;

disposing a barrier plug within a portion of the first and second openings, the barrier plug inducing a tensile stress on the first channel region; and

filling the remaining of the first and second openings with a contact metal.

20. The method of claim 19, wherein the barrier plug is disposed with an intrinsic tensile stress.

21. The method of claim 19, further comprising disposing an adhesion layer in the opening prior to disposing the barrier plug.