SRAM and logic transistors with variable height multi-gate transistor architecture

• US 20080157225A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Yih, Kavalieros, Jack T., Doyle, Brian S., Datta, Suman
• Application Number:
  US11/648,521
• Publication Number:
  US 20080157225A1
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.

Claims

1. An apparatus comprising:

a first multi-gate transistor having a non-planar semiconductor body with first sidewall height; and

a second multi-gate transistor having a non-planar semiconductor body with a second sidewall height, wherein the first multi-gate transistor is in an SRAM cell of a microprocessor.

2. The apparatus of claim 1, wherein the first non-planar semiconductor body sidewall height is greater than the second non-planar semiconductor body sidewall height.

3. The apparatus of claim 2, wherein the second multi-gate transistor is in the SRAM cell.

4. The apparatus of claim 3, wherein the first multi-gate transistor is a pull-down transistor and the second multi-gate transistor is a pass transistor.

5. The apparatus device of claim 4, wherein the first non-planar semiconductor body sidewall height is greater than the second non-planar semiconductor body sidewall height by an amount sufficient to make the channel width of the pull down transistor 1.5 times greater than the channel width of the pass transistor when the first and second non-planar semiconductor bodies have the same top surface width.

6. The apparatus of claim 3, wherein the first multi-gate SRAM transistor and the second multi-gate SRAM transistor are formed from one continuous non-planar semiconductor body having a first region with the first sidewall height adjacent to a second region of the non-planar semiconductor body having the second sidewall height.

7. The apparatus of claim 1, wherein the first and second multi-gate transistors are tri-gate transistors having a channel width equal to the non-planar semiconductor body width added to twice the sidewall height of the non-planar semiconductor body.

8. The apparatus of claim 7, wherein the first multi-gate transistor has a non-planar semiconductor body top surface width which is equal to the non-planar semiconductor body top surface width of the second multi-gate transistor.

9. An apparatus comprising:

a multi-gate SRAM transistor in an integrated circuit having a first non-planar semiconductor body sidewall height and a first non-planar semiconductor body width; and

a multi-gate logic transistor in the integrated circuit having a second non-planar semiconductor body sidewall height and a second width; and

, wherein the first non-planar semiconductor body sidewall height is greater than the second non-planar semiconductor body sidewall height.

10. The apparatus of claim 9, wherein the multi-gate SRAM transistor has a channel width 1.5 times greater than that of the multi-gate logic transistor and the first non-planar semiconductor body width is equal to the second non-planar semiconductor body width.

11. The apparatus of claim 9, wherein the first non-planar semiconductor body width is between 20% and 35% greater than the second non-planar semiconductor body width.

12. The apparatus of claim 9, wherein the first non-planar semiconductor body sidewall height is between 50% and 100% greater than the second non-planar semiconductor body sidewall height.

13. A method of forming a multi-gate SRAM transistor comprising:

forming first isolation region on a bulk semiconductor substrate adjacent to and planar with a pull-down SRAM transistor semiconductor body;

forming a second isolation region on the bulk semiconductor substrate adjacent to and planar with a second semiconductor body;

performing a first etch on both the first isolation region and the second isolation region to expose at least a portion of the sidewalls of both the SRAM transistor semiconductor body and the second transistor semiconductor body;

masking the second isolation region;

performing a second etch on the first isolation region to expose an additional portion of the SRAM transistor semiconductor body sidewalls;

forming a first gate insulator adjacent to the exposed portion of the sidewalls of the pull-down SRAM transistor semiconductor body and forming a second gate insulator adjacent to the exposed portion of the sidewalls of the second transistor semiconductor body;

forming a first gate electrode adjacent to the first gate insulator and forming a second gate electrode adjacent to the second gate insulator; and

forming a first pair of source/drain regions on opposite sides of the first gate electrode and a second pair of source/drain regions on opposite sides of the second gate electrode.

14. The method of claim 13 further comprising:

forming a first gate insulator and first gate electrode on a top surface of the pull-down SRAM transistor semiconductor body to form a tri-gate device; and

forming a second gate insulator and second gate electrode on a top surface of the second transistor semiconductor body to form a tri-gate device.

15. The method of claim 13, wherein the second transistor is a pass transistor in an SRAM cell of a microprocessor.

16. The method of claim 15, wherein the second etch exposes approximately 25% more sidewall than the first etch.

17. The method of claim 13, wherein the second transistor is a logic transistor in a core of a microprocessor.

18. The method of claim 17, wherein the second etch exposes between 50% and 100% more sidewall than the first etch.

19. The method of claim 13, wherein the both the first and second etches are wet chemical etches.

20. The method of claim 19, wherein the wet chemical etches comprises HF.