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SRAM and logic transistors with variable height multi-gate transistor architecture

  • US 20080157225A1
  • Filed: 12/29/2006
  • Published: 07/03/2008
  • Est. Priority Date: 12/29/2006
  • Status: Abandoned Application
First Claim
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1. An apparatus comprising:

  • a first multi-gate transistor having a non-planar semiconductor body with first sidewall height; and

    a second multi-gate transistor having a non-planar semiconductor body with a second sidewall height, wherein the first multi-gate transistor is in an SRAM cell of a microprocessor.

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