Semiconductor device and method of manufacturing the same

• US 20080157234A1
• Filed: 10/31/2007
• Published: 07/03/2008
• Est. Priority Date: 12/27/2006
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Hong, Ji Ho
• Application Number:
  US11/930,293
• Publication Number:
  US 20080157234A1
• Time in Patent Office: Days
• US Class Current: 257/413
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

Provided are a semiconductor device and a method of manufacturing the same. In the semiconductor device, an insulating layer and a polysilicon layer are formed on a substrate, and a notch region is formed at a portion of the polysilicon layer contacting the insulating layer. The widths of the polysilicon layer and the insulating layer are respectively reduced in the notch region.

Claims

1. A semiconductor device comprising:

an insulating layer on a substrate;

a polysilicon layer on the insulating layer; and

a notch region at a portion of the polysilicon layer contacting the insulating layer,

wherein respective widths of the polysilicon layer and the insulating layer are reduced at the notch region.

2. The semiconductor device according to claim 1, wherein the notch region slants toward a center region of the polysilicon layer.

3. The semiconductor device according to claim 1, wherein the insulating layer and the polysilicon layer have a same width in the notch region.

4. The semiconductor device according to claim 1, wherein the notch region is formed on a side of a lower portion of the polysilicon layer and a side of the insulating layer.

5. The semiconductor device according to claim 1, wherein a channel length of the insulating layer is reduced by the notch region.

6. The semiconductor device according to claim 1, wherein the insulating layer and the polysilicon layer provide a gate of a transistor, and a critical dimension of the gate is reduced by the notch region.

7. The semiconductor device according to claim 6, wherein a channel length of the transistor is reduced by the notch region.

8. The semiconductor device according to claim 1, further comprising:

spacers at sides of the polysilicon layer;

source/drain regions on the substrate; and

a silicide layer on the polysilicon layer and the source/drain regions.

9. A method of manufacturing a semiconductor device, comprising:

forming an insulating material, a polysilicon material, and a mask material on a substrate;

performing a first dry etching process to form an insulating layer, a polysilicon layer, and a mask layer; and

performing a second dry etching process using the mask layer as a mask to form a notch region on the insulating layer and a lower region of the polysilicon layer.

10. The method according to claim 9, further comprising:

forming spacers at sides of the polysilicon layer;

forming source/drain regions in the substrate; and

forming a silicide layer on the polysilicon layer and the source/drain regions.

11. The method according to claim 9, wherein the mask material comprises a silicon oxide material.

12. The method according to claim 9, wherein performing the first dry etching process comprises:

using a pressure ranging between 55 and 85 mTorr;

using a source power ranging between 550 and 900 W;

using a bias power ranging between 50 and 70 W; and

using HBr, He, and O₂.

13. The method according to claim 12, wherein using HBr, He, and O₂ comprises using a flow rate of HBr ranging between 320 and 480 sccm, and a flow rate of He/O₂ ranging between 12 and 18 sccm.

14. The method according to claim 9, wherein performing the second dry etching process comprises:

using a pressure ranging between 10 and 14 mTorr;

using a source power ranging between 140 and 210 W;

using a bias power ranging between 50 and 60 W; and

using HBr and O₂.

15. The method according to claim 14, wherein using HBr and O₂ comprises using a flow rate of HBr ranging between 120 and 180 sccm and a flow rate of 02 ranging between 3 and 5 sccm.

16. The method according to claim 9, wherein the notch region slants towards an inner region of the polysilicon layer.

17. The method according to claim 9, wherein a channel length of the insulating layer is reduced by the notch region.

18. The method according to claim 9, wherein by the insulating layer and the polysilicon layer provide a gate structure of a transistor.

19. The method according to claim 18, wherein a critical dimension of the gate structure is reduced by the notch region.

20. The method according to claim 18, wherein a channel length of the transistor is reduced by the notch region.