INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING IMPROVED REACTION BARRIER LAYERS

• US 20080157395A1
• Filed: 12/28/2006
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: Ultratech Incorporated (Veeco Instruments Incorporated)
• Original Assignee: Ultratech Incorporated (Veeco Instruments Incorporated)
• Inventors: Lavoie, Christian, Sullivan, Michael J., Lauro, Paul A., Shih, Da-Yuan, Belanger, Luc, Laine, Eric H., Giri, Ajay P., Kang, Sung Kwon, Buchwalter, Leena Paivikki, Henderson, Donald W., Buchwalter, Stephen L., Griffith, Jonathan H., Srivastava, Kamalesh K., Oberson, Valerie Anne
• Granted Patent: US 8,314,500 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01037 : Rubidium [Rb]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Claims

1. In an interconnection structure suitable for flip-chip attachment of microelectronic device chips to chip carriers, a three-layer ball limiting metallurgy comprising:

an adhesion layer for deposition on a wafer or substrate;

a solder reaction barrier layer of a material selected from the group consisting of Ni, Co, Ru, W, V, Nb, Hf, Mo and their alloys; and

a solder wettable layer.

2. The interconnection structure of claim 1, wherein the adhesion layer is formed of a material selected from the group consisting of TiW, Ti, Cr, Ta, and their alloys.

3. The interconnection structure of claim 1, wherein the solder wettable layer is formed of a material selected from the group consisting of Cu, Pd, Au, Pt, Sn and their alloys.

4. The interconnection structure of claim 1, further comprising fourth layer formed of a material selected from the group consisting of Au and Sn.

5. The interconnection structure of claim 1, wherein said adhesion layer is selected from the group consisting of Ti and TiW, said reaction barrier is selected from the group consisting of Ni and alloys, thereof, and said solder wettable layer is selected from the group consisting of Cu, Sn, Pd, Pt and alloys, thereof.

6. The interconnection structure of claim 5, wherein said Ni alloys are formed by alloying Ni with one or more elements selected from the group consisting of W, Si, Ru, Ti, La, Zr, Hf, V, Cr, Cu, Rh, Ir, Re, Mo, Nb, Ta, Au, Pd and Pt to form a binary, ternary or quaternary alloyed reaction barrier layer.

7. The interconnection structure of claim 6, wherein said the Ni alloy reaction barrier layer is formed by alloying Ni with W to form a binary nonmagnetic NiW alloy layer, wherein W composition is greater than 17 weight percent to facilitate sputter-deposition from a nonmagnetic target.

8. The interconnection structure of claim 6, wherein said the Ni alloy reaction barrier layer is formed by alloying Ni with Si to form a binary nonmagnetic NiSi alloy layer, wherein Si in said alloy is greater than 3.8 weight percent to facilitate sputter-deposition from a nonmagnetic target.

17. The interconnection structure of claim 6, wherein said lead-free solder ball is comprised of a material that substantially avoids alpha particle emission.

18. The interconnection structure of claim 6, wherein said solder alloying components are selected from the group consisting of Sn, Bi, Cu, Ag, Ni, Co, La, Fe and Sb.

9. In an interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, a two-layer ball-limiting metallurgy comprising:

an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion and reaction layer; and

a solder wettable layer;

said adhesion/reaction barrier layer being for placement between a microelectronic device and said solder wettable layer, and wherein said solder wettable layer is of a metal reactive with components of a tin-containing lead-free solder, so that said solder wettable layer is consumed during soldering, wherein the adhesion/reaction barrier layer remains after being placed in contact with said lead free solder during soldering; and

wherein said solder wettable layer is of a metal reactive with components of a tin-containing lead-free solder; and

one or more lead-free solder balls selectively situated on said solder wettable layer, said lead-free solder balls comprising tin as a predominant component and one or more alloying components.

10. The interconnection structure of claim 9, wherein said adhesion/reaction barrier layer is comprised of a material selected from the group consisting of Ti, W, Ta, Cr, V and their alloys.

11. The interconnection structure of claim 9, wherein said solder wetting layer is comprised of a material selected from the group consisting of Cu, Ru, Au, Pd, Pt, Sn and their alloys.

12. The interconnection structure of claim 9, where the adhesion metal is alloyed with one or more element selected from the group consisting of Ti, W, Cu, Ni, Co, Pd, Pt, Au, Zr, Hf and N.

13. An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising:

a two-layer ball-limiting metallurgy comprising an adhesion layer, wherein the adhesion layer serves to promote the adhesion of BLM to the substrate, and a solder reaction barrier/wettable layer, said reaction barrier/wettable layer serving to facilitate both solder wettability and slow solder reaction, the layer being for placement between a microelectronic device and said solder, and wherein said solder reaction barrier/wettable layer is of a metal readily reactive with components of a tin-containing lead-free solder, so that said solder reaction barrier/wettable layer is only partially consumed during soldering, wherein residual unreacted reaction barrier/wettable layer still remains after being placed in contact with said lead free solder during soldering; and

one or more lead-free solder balls selectively situated on said solder wettable layer, said lead-free solder balls comprising tin as a predominant component and one or more alloying components.

14. The interconnection structure of claim 13, wherein said adhesion layer is comprised of a material selected from the group consisting of Cr, TiW, Ti, TiN, TaN, Ta and V.

15. The interconnection structure of claim 13, wherein said solder reaction barrier/wetting layer is comprised of a material selected from the group consisting of Ru, Ni, Co, Pt and alloys thereof.

16. The interconnection structure defined in claim 13, further comprising third layer comprised of Au or Sn.

20. The interconnection structure defined in claim 13, wherein said solderable layer is formed of a material selected from the group consisting of Cu, Ni, Co, Pd, Ru, Au, Pt, Sn and alloys thereof.

19. An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising:

a three-layer ball-limiting composition comprising an adhesion layer, a reaction barrier layer on top of said adhesion layer and a solder wettable layer, wherein said adhesion/barrier layer is between a microelectronic device and said solder wettable layer and wherein said solder wettable layer is of a composition sufficiently reactive with components of a tin-containing lead free solder, and the reaction barrier layer is substantially less-reactive with solder after being placed in contact therewith in a solder joining process; and

one or more lead-free solder balls selectively situated on said solder wettable layer, said lead-free solder balls having tin as a predominant component and one or more alloying components selected from the group consisting of Cu, Ag, Bi, Co, La, Fe, Ni and Sb, whereby said lead-free solder ball substantially avoids alpha particle emission and induced soft logic errors which result therefrom.

34. A method as recited in claim 19, further comprising annealing the ball limiting metallurgy at 150-350 degrees C. for 30 to 90 minutes.

21. A method for forming an interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising:

forming a ball limiting metallurgy on a substrate;

forming a resist pattern on the ball limiting metallurgy;

etching the ball limiting metallurgy by using the resist pattern as an etch mask;

removing the resist from remaining ball limiting metallurgy; and

depositing solder on the ball limiting composition.

22. A method as recited in claim 21, wherein the solder is substantially lead free.

23. A method as recited in claim 21, wherein the ball limiting metallurgy is formed by:

depositing an adhesion layer on said substrate;

depositing a reaction barrier layer on said adhesion layer; and

depositing a solder wettable layer on said barrier layer.

24. A method as recited in claim 23, wherein said reaction barrier layer is comprised of a material selected from the group consisting of Ni, Co, W, Ru, Nb, V, Mo, Hf and alloys thereof.

25. A method as recited in claim 23, wherein said adhesion layer is deposited by sputtering or evaporation.

26. A method as recited in claim 23, wherein said adhesion layer is deposited so as to have a thickness of about 100 to about 5000 Angstroms.

27. A method as recited in claim 23, wherein said reaction barrier layer is deposited by sputtering, plating or evaporation.

28. A method as recited in claim 27, wherein said reaction barrier layer is deposited so as to have a thickness of about 1000 to about 40,000 angstroms.

29. A method as recited in claim 23, wherein said solder wettable layer is deposited by sputtering, plating or evaporation.

30. A method as recited in claim 23, wherein said solder wettable layer is deposited so as to have a thickness of about 200 to about 20,000 angstroms.

31. A method as recited in claim 23, further comprising depositing a layer comprising Au or Sn on said solder wettable layer.

32. A method as recited in claim 31, wherein the layer deposited on said solder wettable layer has a thickness of between substantially 100 to substantially 20,000 angstroms.

33. A method as recited in claim 31, wherein the layer deposited on said solder wettable layer is deposited by one of sputtering, electro- or electroless plating or evaporation.

35. A method for forming an interconnection structure suitable for flip-chip attachment of microelectronic device chips to chip carriers, comprising:

depositing an adhesion layer on a wafer or substrate serving as said chip carrier;

depositing a solder reaction barrier layer on said adhesion layer;

depositing a solder wettable layer on said reaction barrier layer;

depositing a lead free solder on said solder wettable layer; and

reflowing said solder so that said solder wettable layer diffuses into said lead free solder.

36. A method as recited in claim 35, wherein said solder wettable layer contains Cu, and said Cu diffuses into said solder.

37. A method as recited in claim 35, wherein said lead free solder is substantially pure Sn, and a binary Sn—

Cu lead-free solder is formed during reflowing.

38. A method as recited in claim 35, wherein said lead free solder is substantially binary Sn—

Ag, and a ternary Sn—

Ag—

Cu lead-free solder is formed during reflowing.

39. A method as recited in claim 35, wherein a near eutectic binary or ternary solder is formed.

40. A method as recited in claim 35, further comprising annealing BLM at 150-350 degrees C. for 30 to 90 minutes.