Adaptive pole and zero and pole zero cancellation control low drop-out voltage regulator

• US 20080157735A1
• Filed: 04/09/2007
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Abandoned Application

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lin, Chung-Wei, Lee, Yung-Pin, Liu, Yen-Jen
• Application Number:
  US11/783,357
• Publication Number:
  US 20080157735A1
• Time in Patent Office: Days
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A adaptive pole and zero and Pole-Zero Cancellation Control Low Drop-Out (LDO) regulator is provided, which includes a regulation unit, an error amplifier, a Miller Effect Pole control unit, a Pole Zero Cancellation delay unit, and a feedback network. Pole and Zero could be adaptive regulated depend on various loads and maintain stably in a perfect phase margin.

Claims

1. An adaptive pole and zero and pole-zero cancellation control LDO regulator, comprising:

a regulation unit, including an input node, an output node, and a control node, wherein the input node of the regulation unit receives an input signal, the regulation unit responds a control signal received by the control node, and the regulation unit provides an output signal through the output node;

an error amplifier, including an inverting input node connecting to a reference voltage and an output node connecting to a first node;

a Miller Effect Pole control unit, including a p-type metal oxide semiconductor (PMOS) connecting to a n-type metal oxide semiconductor (NMOS), wherein a source of the PMOS connects to the input node, a gate of the PMOS connects to the first node and the control node, a drain of the PMOS connects to a drain and gate of the NMOS in series through a second node and a source of the NMOS is grounding;

a Pole-Zero Cancellation delay unit, connecting to the first node, the second node and the control node; and

a feedback network, connecting to the output node and a non inverting output node of the error amplifier.

2. The LDO regulator of claim 1, wherein the regulation unit is a p-type metal oxide semiconductor or an n-type metal oxide semiconductor.

3. The LDO regulator of claim 1, wherein the Pole-Zero Cancellation delay unit further includes a buffer, wherein an inverting input node of the buffer connects to the control node;

and a resistor-capacitor series connection connecting to the first node and the second node wherein the first node is used as a non inverting input node of the buffer.

4. The LDO regulator of claim 3, wherein the first node further parallel connects to a resistor-capacitor parallel connection.

5. The LDO regulator of claim 4, wherein P1 is obtained by following formula

$P$



1 = 1 2 

π





C 



1 



( 1 + gm 



1 / gm 



2 ) 



R2 ;

wherein C1 is a capacitance value for resistor of the resistor-capacitor series connection, gm1 is a first transconductance of the PMOS, gm2 is a second transconductance of the NMOS, and R2 is an equivalent resistance outputted by the error amplifier.

6. The LDO regulator of claim 4, wherein P2 is obtained by following formula:

$P<br><br><br><br>2=\frac{1}{2<br><br>\mathrm{\pi <br><br>}<br><br><br><br>C<br><br><br><br>2<br><br>\frac{R<br><br><br><br>1}{\left(1+\mathrm{gm}<br><br><br><br>1/\mathrm{gm}<br><br><br><br>2\right)}},$

wherein C2 is an equivalent capacitance outputted by the error amplifier, gm1 is a first transconductance of the PMOS, gm2 is a second transconductance of the NMOS, and R1 is a resistance value for resistor of the resistor-capacitor series connection.

7. The LDO regulator of claim 4, wherein P2 is obtained by following formula:

$Z<br><br><br><br>1=\frac{1}{2<br><br>\mathrm{\pi <br><br>}<br><br><br><br>C<br><br><br><br>1<br><br><br><br>\left(R<br><br><br><br>1+\frac{1}{\mathrm{gm}<br><br><br><br>2}\right)},$

wherein C1 is a capacitance value for capacitance of the resistor-capacitor series connection, gm2 is a second transconductance of the NMOS, and R1 is a resistance value for resistance of the resistor-capacitor series connection.

8. The LDO regulator of claim 1, wherein the feedback network is a voltage divider, wherein one voltage divided node connects to the non inverting input node of the error amplifier.