Systems and Methods for Adding a Delay to a Signal

• US 20080157840A1
• Filed: 12/29/2007
• Published: 07/03/2008
• Est. Priority Date: 12/31/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sperlich, Roland, Atrash, Amer Hani
• Granted Patent: US 7,814,450 B2
• Time in Patent Office: Days
• US Class Current: 327/161
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination is made in response to determining the path length to the device.

Claims

1. A method for transmitting a signal, the method comprising:

determining a signal path length to a device over a transmission line; and

adding a delay to a signal to be transmitted over the transmission line in response to the determining the signal path length to the device, the signal having a desired phase at the device.

2. The method of claim 1, where the signal is an electrical clock signal.

3. The method of claim 2, where the electrical clock signal is generated using a phase-locked loop and a voltage-controlled crystal oscillator.

4. The method of claim 1, further comprising:

determining additional signal path lengths to additional devices over additional transmission lines; and

adding delays to additional signals to be transmitted over the additional transmission lines in response to the determining the additional signal path lengths to the additional devices, the additional signals having desired phases at each of the devices.

5. The method of claim 4, further comprising adjusting the delay and the additional delays such that the signal and the additional signals have equal phase at each of the devices.

6. The method of claim 1, where the determining the signal path length comprises:

sending a signal pulse on the transmission line;

receiving a reflection of the signal from the device; and

computing the signal path length by determining a roundtrip time and amplitude for the signal.

7. The method of claim 6, further comprising:

receiving false reflections of the signal; and

detecting and ignoring the false reflections of the signal using an estimated roundtrip time and an estimated amplitude for the signal.

8. The method of claim 1, where the adding the delay comprises adding the delay using a delay-locked loop.

9. An apparatus comprising:

a delay controller; and

a delay generator coupled to the delay controller, the delay generator being configured to couple to a transmission line, the transmission line coupling a signal generator and a device;

the delay controller being configured to determine a signal path length from the signal generator to the device; and

the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.

10. The apparatus of claim 9, where the signal is an electrical clock signal.

11. The apparatus of claim 10, where the signal generator comprises a phase-locked loop coupled to a voltage-controlled crystal oscillator for generating the electrical clock signal.

12. The apparatus of claim 9, where:

the delay controller is further configured to determine additional signal path lengths of additional transmission lines, the additional transmission lines coupling the signal generator to additional devices; and

additional delay generators coupled to the additional transmission lines are configured to add additional delays to additional signals to be transmitted over the additional transmission lines in response to the delay controller determining the additional signal path lengths to the additional devices, the signals having additional desired phases at each of the additional devices.

13. The apparatus of claim 12, where the delay controller is further configured to adjust the delay and the additional delays such that the signal and the additional signals have equal phases at each of the devices.

14. The apparatus of claim 9, where the delay controller being configured to determine the signal path length comprises the system being configured to:

send a signal pulse on the transmission line;

receive a reflection of the signal from the device; and

compute the signal path length by determining a roundtrip time and amplitude for the signal.

15. The apparatus of claim 14, the delay controller is further configured to:

receive false reflections of the signal; and

detect and ignore the false reflections of the signal using an estimated roundtrip time and amplitude for the signal.

16. The apparatus of claim 9, where the delay generator comprises a delay-locked loop.

17. A computer program product stored on a computer operable medium, the computer program product comprising software code being effective to:

determine a signal path length to a device over a transmission line; and

cause a delay to be added to a signal to be transmitted over a transmission line in response to the code being effective to determine the signal path length to the device, the signal having a desired phase at the device.

18. The product of claim 17, where the signal is an electrical clock signal.

19. The product of claim 18, where the electrical clock signal is generated using a phase-locked loop and a voltage-controlled crystal oscillator.

20. The product of claim 17, where the code is further configured to:

determine additional signal path lengths to additional devices over additional transmission lines; and

add additional delays to additional signals to be transmitted over the additional transmission lines in response to the code being effective to determine the additional signal path lengths to the additional devices, the additional signals having additional desired phases at each of the additional devices.

21. The product of claim 20, where the code is further effective to adjust the delay and the additional delays such that the signal and the additional signals have equal phases at each of the device and the additional devices.

22. The product of claim 17, where the code being effective to determine the signal path length comprises the code being effective to:

cause a signal pulse to be sent on the transmission line;

cause a reflection of the signal from the device to be detected; and

compute the signal path length by determining a roundtrip time and amplitude for the signal.

23. The product of claim 22, the code is further effective to:

cause a detection of additional false reflections of the signal; and

cause the false reflections of the signal to be detected and ignored using an estimated roundtrip time and amplitude for the signal.

24. The product of claim 17, where the code being effective to add the delay comprises the code being configured to cause the delay to be added using a delay-locked loop.

25. An information handling system comprising:

one or more processors;

a memory unit coupled to the one or more processors;

a communications device coupled to the one or more processors; and

a delay device coupled to the one or more processors, the delay device comprising;

a delay controller; and

a delay generator coupled to the delay controller, the delay generator being configured to couple to a transmission line, the transmission line coupling a signal generator and a device;

the delay controller being configured to determine a signal path length from the signal generator to the device; and

the delay generator being configured to add a delay to a signal to be transmitted over the transmission line in response to the delay controller determining the signal path length to the device, the signal having a desired phase at the device.

26. The information handling system of claim 25, where the signal is an electrical clock signal.

27. The information handling system of claim 26, where the signal generator comprises a phase-locked loop coupled to a voltage-controlled crystal oscillator for generating the electrical clock signal.