Shift register and liquid crystal display device using same
First Claim
Patent Images
1. A shift register for providing a plurality of low level shift register signals, the shift register comprising:
- a plurality of shift register units connected in series, each shift register unit comprising a first inversion circuit, a second inversion circuit, and a third inversion circuit;
the first inversion circuit being configured for providing a second output signal according to a clock signal from an external circuit and a first output signal from the third inversion circuit;
the second inversion circuit being configured for providing a control signal according to a first output signal from a previous adjacent one of the shift register units and a second output signal from the previous adjacent shift register unit, except in the case of a first one of the shift register units, wherein the second inversion circuit is configured for providing a control signal according to a first external output signal from an external circuit and a second external out put signal from an external circuit;
the third inversion circuit being configured for providing the first output signal and a shift register signal according to the control signal, the second output signal and an inverse clock signal from the external circuit;
wherein the two first inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, the two third inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, and the first shift register unit receives a start signal from an external circuit to start the shift register.
4 Assignments
0 Petitions
Accused Products
Abstract
An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.
-
Citations
16 Claims
-
1. A shift register for providing a plurality of low level shift register signals, the shift register comprising:
-
a plurality of shift register units connected in series, each shift register unit comprising a first inversion circuit, a second inversion circuit, and a third inversion circuit; the first inversion circuit being configured for providing a second output signal according to a clock signal from an external circuit and a first output signal from the third inversion circuit; the second inversion circuit being configured for providing a control signal according to a first output signal from a previous adjacent one of the shift register units and a second output signal from the previous adjacent shift register unit, except in the case of a first one of the shift register units, wherein the second inversion circuit is configured for providing a control signal according to a first external output signal from an external circuit and a second external out put signal from an external circuit; the third inversion circuit being configured for providing the first output signal and a shift register signal according to the control signal, the second output signal and an inverse clock signal from the external circuit; wherein the two first inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, the two third inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, and the first shift register unit receives a start signal from an external circuit to start the shift register. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A shift register for providing a plurality of low level shift register signals, the shift register comprising a plurality of shift register units connected in series, each shift register unit comprising a first inversion circuit, a second inversion circuit, and a third inversion circuit;
-
the first inversion circuit comprising a first transistor and a second transistor, a source of the first transistor being coupled to a high level voltage, a drain of the first transistor being coupled to a drain of the second transistor, a source of the second transistor being coupled to a low level voltage, a gate of the first transistor being coupled to the third inversion circuit, and a gate of the second transistor being coupled to a clock signal source; the second inversion circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a source of the third transistor being coupled to the low level voltage, a drain of the third transistor being coupled to a source of the fourth transistor, a gate of the fourth transistor being coupled to the low level voltage, a source of the sixth transistor being coupled to the high level voltage and being coupled to the source of the fourth transistor via a drain of the sixth transistor, a gate of the fifth transistor being coupled to the drain of the first transistor, a drain of the fifth transistor being coupled to a first output of a previous adjacent one of the shift register units, except in the case of a first one of the shift register units, wherein the drain of the fifth transistor coupled to an external circuit; the third inversion circuit comprising a seventh transistor and an eighth transistor, a source of the seventh transistor being coupled to an inverse clock signal source and being coupled to the high level voltage via a drain of the seventh transistor and a source and a drain of the eighth transistor, a gate of the seventh transistor being coupled to the drain of the fourth transistor, a gate of the eighth transistor being coupled to the gate of the fifth transistor; wherein the two first inversion circuits of two adjacent shift register units receive the clock signal and the inverse clock signal, and the two third inversion circuits of the two adjacent shift register units receive the clock signal and the inverse clock signal, and the first shift register unit receives a start signal from the external circuit to start the shift register. - View Dependent Claims (9, 10, 11, 12)
-
-
13. A liquid crystal display comprising:
-
a liquid crystal panel; a gate driving circuit; and a data driving circuit; each of the gate driving circuit and the data driving circuit comprising at least one shift register, each of the shift registers comprising a plurality of shift register units, each shift register unit comprising a first inversion circuit, a second inversion circuit, and a third inversion circuit; the first inversion circuit being configured for providing a second output signal according to a clock signal from an external circuit and a first output signal from the third inversion circuit; the second inversion circuit being configured for providing a control signal according to a first output signal from a previous adjacent one of the shift register units and a second output signal from the previous adjacent shift register unit, except in the case of a first one of the shift register units, wherein the second inversion circuit is configured for providing a control signal according to a first external output signal from an external circuit and a second external output signal from an external circuit; the third inversion circuit being configured for providing the first output signal and a shift register signal according to the control signal, the second output signal and an inverse clock signal from the external circuit; wherein the two first inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, the two third inversion circuits of adjacent shift register units respectively receive the clock signal and the inverse clock signal, and the first shift register unit receives a start signal from an external circuit to start the shift register. - View Dependent Claims (14, 15, 16)
-
Specification