HARDWARE ARCHITECTURE FOR VIDEO CONFERENCING

• US 20080158338A1
• Filed: 11/19/2007
• Published: 07/03/2008
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Tandberg Products UK Ltd. (Cisco Systems, Inc.)
• Original Assignee: Tandberg Products UK Ltd. (Cisco Systems, Inc.)
• Inventors: EVANS, Simon J.W.
• Granted Patent: US 7,889,226 B2
• Time in Patent Office: Days
• US Class Current: 348/14.09
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: H04N 7/152 Multipoint control units therefor

Abstract

Video processing architectures, systems, and methods for a multipoint control unit are provided. In one example, a video processing system includes a motherboard and at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, where the daughterboard switch is configured to switch data between the plurality of processors and between the motherboard and daughterboard. The video processing system may further include a plurality of daughterboards each having an identical hardware and/or mechanical configuration. The plurality of daughterboards may be configured to be mechanically and electrically couplable together in any order, and may be stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along said series chain.

Claims

1. A video processing system for a multipoint control unit, the video processing system comprising:

a motherboard; and

at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, the daughterboard switch configured to switch data between the plurality of processors and between the motherboard and daughterboard.

2. The video processing system of claim 1, further comprising a plurality of daughterboards each having an identical hardware configuration.

3. The video processing system of claim 1, further comprising a plurality of daughterboards each having an identical mechanical configuration.

4. The video processing system of claim 1, further comprising a plurality of daughterboards configured to be mechanically and electrically couplable together in any order.

5. The video processing system of claim 1, further comprising a plurality of daughterboards stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along the series chain.

6. The video processing system of claim 1, further comprising a plurality of daughterboards, wherein the motherboard comprises a motherboard switch arranged to switch data between a plurality of the daughterboards.

7. The video processing system of claim 1, wherein the motherboard comprises a motherboard switch arranged to switch data between a plurality of the daughterboards.

8. The video processing system of claim 7, wherein the motherboard switch comprises at least part of a field programmable gate array.

9. The video processing system of claim 1, wherein the daughterboard switch comprises at least part of a field programmable gate array.

10. The video processing system of claim 1, wherein the plurality of processors comprise digital signal processors.

11. A method for processing video in a multipoint control unit having a motherboard and at least one daughterboard, each of the at least one daughterboard having a plurality of processors interconnected via a daughterboard switch, the method comprising:

switching data between the plurality of processors associated with the daughterboard and between the motherboard and daughterboard.

12. The method of claim 11, wherein the method further comprises switching data to a daughterboard switch on another daughterboard to permit data flow along a series chain of daughterboards.

13. The method of claim 11, wherein the motherboard comprises a motherboard switch operable to switch data between a plurality of daughterboards.

14. A video processing system for a multipoint control unit, comprising:

a plurality of processors adapted to perform processing of data representative of video images;

a plurality of links interconnecting the plurality of processors; and

a stream processor configured to process data as it passes between the plurality of processors over the links.

15. The video processing system according to claim 14, wherein the stream processor forms part of a field programmable gate array.

16. The video processing system according to claim 15, wherein the stream processor is associated with a memory co-located on the field programmable gate array.

17. The video processing system according to claim 16, wherein the stream processor has predetermined logic and is also at least partially programmable in operation, by loading one or both of bit masks and data into said memory.

18. The video processing system according to claim 15, wherein the stream processor is associated with a memory that is external to the field programmable gate array.

19. The video processing system according to claim 18, wherein the stream processor has predetermined logic and is also at least partially programmable in operation, by loading one or both of bit masks and data into said memory.

20. The video processing system according to claim 14, wherein the stream processor is operable to perform bandwidth compression on a video stream passing through the processor.

21. The video processing system according to claim 20, wherein the stream processor is associated with a memory and which is operable to store historical information about previous portions of the video stream which have passed through the processor.

22. The video processing system according to claim 14, wherein the stream processor is arranged to perform bandwidth de-compression on a video stream passing through the processor.

23. The video processing system according to claim 14, further comprising a plurality of said stream processors.

24. A method of transmitting a scaled video image to different destinations at different respective scaling levels with an MCU including a plurality of processors operable to perform processing of data representative of video images, the plurality of processors interconnected by a plurality of links, and a plurality of stream processors operable to process data as it passes between the processors over the plurality of links, the method comprising:

performing video scaling of video data in a first of the stream processors to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination.

25. A method according to claim 24, comprising storing a network map holding data representative of a network topology of the architecture and making scaling decisions with reference to the map.

26. A computer readable medium encoded with computer program instructions for routing video data in a multipoint control unit having a plurality of signal processors, the computer program instructions comprising:

instructions for performing video scaling of video data in a first stream processors to a first scale level required by a first destination and performing subsequent scaling of the video data using a second stream processor to a second, smaller scaling level for a second destination.

27. The computer readable medium of claim 26, wherein the computer program instructions further comprise storing a network map holding data representative of a network topology of the architecture and making scaling decisions with reference to the map.

28. A video processing system for a multipoint control unit, comprising:

a plurality of processors adapted to perform processing of data representative of video images, the plurality of processors being interconnected via switches operable to choose between unicast and multicast transmission of received data.

29. The video processing system according to claim 28, further comprising a topology store which contains data representative of the links between the processors and wherein the switches access the topology store to make routing decisions and also to make the choice between unicast or multicast transmission of data.

30. The video processing system according to claim 28, further comprising a topology store which contains data representative of the links between the processors and a controller operable to attach routing information to data related to a desired route across the links before the data is transmitted.

31. A method of routing video data in a multipoint control unit having a plurality of signal processors, the method comprising:

storing or retrieving a network map holding data representative of a network topology which interconnects the signal processors; and

selectively switching one or more of a plurality of switches to switch data between the signal processors in unicast or multicast mode dependent on the network map.

32. The method of claim 31, further comprising transmitting information in unicast mode until a routing branch is reached at which data needs to follow a plurality of links and then transmitting information in multicast mode at that routing branch.

33. A computer readable medium encoded with computer program instructions for routing video data in a multipoint control unit having a plurality of signal processors, the computer program instructions comprising:

instructions for storing a network map holding data representative of a network topology which interconnects the signal processors; and

instructions for selectively switching one or more of a plurality of switches to switch data between the signal processors in unicast or multicast mode dependent on the network map.