LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD OF THE SAME

• US 20080158457A1
• Filed: 12/19/2007
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Hwang, Inho, Park, Daelim, Jung, Boyoung
• Granted Patent: US 8,670,098 B2
• Time in Patent Office: Days
• US Class Current: 349/39
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

A fringe field type liquid crystal display panel that increases an aperture ratio of a pixel area includes: a gate line disposed on a substrate; a data line disposed to cross the gate line, wherein a gate insulating film is disposed the gate line and the data line; a thin film transistor disposed at an intersection area of the gate line and the data line; a pixel electrode disposed on the gate insulating film and directly connected to the thin film transistor; a passivation film disposed on the gate insulating film to cover the pixel electrode and the thin film transistor; and a common electrode disposed to overlap the pixel electrode and the data line on the passivation film to form a fringe field for aligning liquid crystal together with the pixel electrode.

Claims

1. A fringe field type liquid crystal display panel, comprising:

a gate line disposed on a substrate;

a data line disposed to cross the gate line, wherein a gate insulate is disposed between the gate line and the date line;

a thin film transistor disposed at an intersection area of the gate line and the data line;

a pixel electrode disposed on the gate insulating film and directly connected to the thin film transistor;

a passivation film disposed on the gate insulating film to cover the pixel electrode and the thin film transistor; and

a common electrode disposed to overlap the pixel electrode and the data line on the passivation film to form a fringe field for aligning liquid crystal together with the pixel electrode.

2. The fringe field type liquid crystal display panel according to claim 1, further comprising:

a storage capacitor having a storage electrode simultaneously disposed and of the same material as the gate line, wherein the pixel electrode is disposed to overlap the storage electrode, and the gate insulating film is disposed between the storage electrode and the pixel electrode.

3. The fringe field type liquid crystal display panel according to claim 1, further comprising:

a gate pad having a gate pad lower electrode connected to the gate line and a gate pad upper electrode connected to the gate pad lower electrode through a first contact hole defined in the passivation film; and

a data pad having a data pad lower electrode connected to the data line and a data pad upper electrode connected to the data pad lower electrode through a second contact hole defined in the passivation film.

4. The fringe field type liquid crystal display panel according to claim 3, wherein the gate pad lower electrode is simultaneously disposed and of the same material as the gate line, and the gate pad upper electrode is simultaneously disposed and of the same material as the common electrode.

5. The fringe field type liquid crystal display panel according to claim 3, wherein the data pad lower electrode is simultaneously disposed and of the same material as the data line, and the data pad upper electrode is simultaneously disposed and of the same material as the common electrode.

6. The fringe field type liquid crystal display panel according to claim 1, wherein the thin film transistor includes:

a gate electrode connected to the gate line;

a source electrode connected to the data line;

a drain electrode which faces the source electrode with a channel therebetween and is directly connected to the pixel electrode at the same time; and

a semiconductor pattern which is disposed to overlap the gate electrode with the gate insulating film therebetween and which has an ohmic contact layer and an active layer that forms a channel between the source electrode and the drain electrode.

7. The fringe field type liquid crystal display panel according to claim 6, wherein the source electrode is disposed to be projected from the data line, and the drain electrode is disposed in a shape to face the source electrode with the channel therebetween.

8. The fringe field type liquid crystal display panel according to claim 6, wherein the source electrode is disposed to be projected from the data line, the drain electrode is disposed in a “

—

”

shape to face the source electrode with the channel therebetween, and a “

—

”

shaped channel is disposed between the source electrode and the drain electrode.

9. The fringe field type liquid crystal display panel according to claim 6, wherein the source electrode is disposed in a “

U”

shape to be projected from the data line, the drain electrode is disposed to face the source electrode with the channel therebetween, and a “

U”

shaped channel is disposed between the source electrode and the drain electrode.

10. The fringe field type liquid crystal display panel according to claim 6, wherein the source electrode is disposed to be integrated with the data line, and the drain electrode is disposed in a shape to face the source electrode with the channel therebetween.

11. The fringe field type liquid crystal display panel according to claim 1, wherein the pixel electrode is disposed with a gap of about 0-3.0 μ

m from the data line 120.

12. The fringe field type liquid crystal display panel according to claim 1, wherein the passivation film comprises an inorganic insulating material of not less than 6000 Å

in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

13. The fringe field type liquid crystal display panel according to claim 1, wherein the passivation film comprises an organic insulating material of not less than 1.5 μ

m in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

14. The fringe field type liquid crystal display panel according to claim 1, wherein the common electrode is disposed to cover an area where the thin film transistor is disposed.

15. The fringe field type liquid crystal display panel according to claim 1, wherein the common electrode is patterned to have a slit groove where a fringe field is formed together with the pixel electrode.

16. The fringe field type liquid crystal display panel according to claim 1, wherein the common electrode comprises a transparent conductive material such as ITO, IZO or the like.

17. A fabricating method of a fringe field type liquid crystal display panel, comprising the steps of:

forming a gate line on a substrate;

forming a data line which crosses the gate line to define a pixel area, wherein a gate insulating film is disposed between the gate line and the data line;

forming a thin film transistor at an intersection area of the gate line and the data line;

forming a pixel electrode on the gate insulating film to be directly connected to the thin film transistor;

forming a passivation film on the gate insulating film to cover the pixel electrode and the thin film transistor; and

forming a common electrode to overlap the pixel electrode and the data line on the passivation film and to form a fringe field for aligning liquid crystal together with the pixel electrode.

18. The fabricating method according to claim 17, further comprising the steps of:

forming a storage capacitor having a storage electrode simultaneously formed of the same material as the gate line, wherein the pixel electrode is formed to overlap the storage electrode and a gate insulating film is formed between the storage electrode and the pixel electrode.

19. The fabricating method according to claim 17, further comprising the steps of:

forming a gate pad having a gate pad lower electrode connected to the gate line and a gate pad upper electrode connected to the gate pad lower electrode through a first contact hole defined in the passivation film; and

forming a data pad having a data pad lower electrode connected to the data line and a data pad upper electrode connected to the data pad lower electrode through a second contact hole defined in the passivation film.

20. The fabricating method according to claim 19, wherein the gate pad lower electrode is simultaneously formed of the same material as the gate line, and the gate pad upper electrode is simultaneously formed of the same material as the common electrode.

21. The fabricating method according to claim 19, wherein the data pad lower electrode is simultaneously formed of the same material as the data line, and the data pad upper electrode is simultaneously formed of the same material as the common electrode.

22. The fabricating method according to claim 17, wherein the thin film transistor includes:

a gate electrode connected to the gate line;

a source electrode connected to the data line;

a drain electrode which faces the source electrode with a channel therebetween and is directly connected to the pixel electrode at the same time; and

a semiconductor pattern which is formed to overlap the gate electrode with the gate insulating film therebetween and which has an ohmic contact layer and an active layer that forms a channel between the source electrode and the drain electrode.

23. The fabricating method according to claim 22, wherein the source electrode is formed to be projected from the data line, and the drain electrode is formed in a shape to face the source electrode with the channel therebetween.

24. The fabricating method according to claim 22, wherein the source electrode is formed to be projected from the data line, the drain electrode is formed in a “

—

”

shape to face the source electrode with the channel therebetween, and a “

—

”

shaped channel is formed between the source electrode and the drain electrode.

25. The fabricating method according to claim 22, wherein the source electrode is formed in a “

U”

shape to be projected from the data line, the drain electrode is formed to face the source electrode with the channel therebetween, and a “

U”

shaped channel is formed between the source electrode and the drain electrode.

26. The fabricating method according to claim 22, wherein the source electrode is formed to be integrated with the data line, and the drain electrode is formed in a shape to face the source electrode with the channel therebetween.

27. The fabricating method according to claim 17, wherein the pixel electrode is formed with a gap of about 0-3.0 μ

m from the data line 120.

28. The fabricating method according to claim 17, wherein the passivation film is formed of an inorganic insulating material of not less than 6000 Å

in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

29. The fabricating method according to claim 17, wherein the passivation film comprises an organic insulating material of not less than 1.5 μ

m in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

30. The fabricating method according to claim 17, wherein the common electrode is formed to cover an area where the thin film transistor is formed.

31. The fabricating method according to claim 17, wherein the common electrode is patterned to have a slit groove where a fringe field is formed together with the pixel electrode.

32. The fabricating method according to claim 17, wherein the common electrode comprises a transparent conductive material such as ITO, IZO or the like.

33. A fabricating method of a fringe field type liquid crystal display panel, comprising the steps of:

forming a first conductive pattern having a gate line, a gate electrode and a gate pad lower electrode, which are connected to the gate line, and the storage electrode on a substrate;

forming a gate insulating film which covers the substrate where the first conductive pattern is formed;

forming a pixel electrode which forms a fringe field on the gate insulating film;

forming a semiconductor layer comprising an ohmic contact layer and an active layer, which forms a channel, on the gate insulating film where the pixel electrode is formed;

forming a second conductive pattern having a data line, which crosses the gate line on the gate insulating film to define a pixel area, a source electrode connected to the data line, a drain electrode formed to face the source electrode with a channel therebetween, and a data pad lower electrode, and a semiconductor pattern having the ohmic contact layer and the active layer which forms the channel;

forming a passivation film to cover the insulating film where the semiconductor pattern and the second conductive pattern are formed; and

forming a common electrode to overlap the pixel electrode and the data line on the passivation film and to form a fringe field.

34. The fabricating method according to claim 33, further comprising the steps of:

forming a storage capacitor having a storage electrode and the pixel electrode which is formed to overlap the storage electrode with the gate insulating film, wherein the gate insulating film is formed between the storage electrode and the pixel electrode.

35. The fabricating method according to claim 33, wherein forming the first conductive pattern includes the steps of:

forming a gate metal layer on the entire surface of the substrate;

forming a photo-resist pattern which exposes a remaining area except an area where the first conductive pattern is to be formed after forming a photo-resist on the surface of the gate metal layer; and

forming the first conductive pattern by etching the gate metal layer exposed by the photo-resist pattern.

36. The fabricating method according to claim 33, wherein forming the second conductive pattern includes the steps of:

forming a data metal layer on the surface of the gate insulating film where the semiconductor layer is formed;

forming a photo-resist pattern having a stepped difference in the channel area by a designated mask process after forming a photo-resist on the entire surface of the data metal layer;

sequentially etching the data metal layer exposed by the photo-resist pattern and the semiconductor layer having the active layer and the ohmic contact layer;

forming a source electrode and a drain electrode which face each other with the channel area therebetween and which are connected to the data line by etching the exposed data metal layer after exposing the data metal layer formed in the channel area by ashing the photo-resist pattern; and

exposing the active layer, which forms a channel, by etching the ohmic contact layer exposed in the channel area as the source and the drain electrodes are separated.

37. The fabricating method according to claim 36, wherein the source electrode is formed to be projected from the data line, and the drain electrode is formed in a shape to face the source electrode with the channel therebetween and to be directly connected to the pixel electrode at the same time.

38. The fabricating method according to claim 36, wherein the source electrode is formed to be projected from the data line, the drain electrode is formed in a “

—

”

shape to face the source electrode with the channel therebetween and to be directly connected to the pixel electrode at the same time, and a “

—

”

shaped channel is formed between the source electrode and the drain electrode.

39. The fabricating method according to claim 36, wherein the source electrode is formed in a “

U”

shape to be projected from the data line, the drain electrode is formed to face the source electrode with the channel therebetween, and a “

U”

shaped channel is formed between the source electrode and the drain electrode.

40. The fabricating method according to claim 36, wherein the source electrode is formed to be integrated with the data line, and the drain electrode is formed in a shape to face the source electrode with the channel therebetween and to be directly connected to the pixel electrode at the same time.

41. The fabricating method according to claim 33, wherein the pixel electrode is formed with a gap of about 0-3.0 μ

m from the data line 120.

42. The fabricating method according to claim 33, wherein forming the passivation film includes the steps of:

forming the passivation film which covers the second conductive pattern on the gate insulating film;

forming a photo-resist pattern which exposes an area where a contact hole is to be defined by a designated mask process after forming a photo-resist on the surface of the passivation film; and

defining a first contact hole which exposes the gate pad lower electrode and a second contact hole which exposes the data pad lower electrode by etching an area exposed by the photo-resist pattern.

43. The fabricating method according to claim 42, wherein the passivation film is formed of an inorganic insulating material of not less than 6000 Å

in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

44. The fabricating method according to claim 42, wherein the passivation film comprises an organic insulating material of not less than 1.5 μ

m in order to prevent a parasitic capacitance from being generated between the common electrode and the drain electrode.

45. The fabricating method according to claim 33, wherein the common electrode comprises a transparent conductive material such as ITO, IZO or the like.