Flash EEPROM System

• US 20080158995A1
• Filed: 10/24/2007
• Published: 07/03/2008
• Est. Priority Date: 04/13/1989
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay
• Application Number:
  US11/923,505
• Publication Number:
  US 20080158995A1
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1-80. -80. (canceled)

81. A memory device comprising:

internal circuitry configured to program reference cells within the memory device, wherein said internal circuitry utilizes existing array cell to reference cell comparison circuitry for determining a program level of at least one of said reference cells.

82. A method of programming a reference cell in a device, comprising the step of:

programming a threshold voltage of said reference cell utilizing internal circuitry of the device, wherein said step of programming a threshold level includes the step of applying array cell programming circuitry to said at least one reference cell to program said at least one reference cell.

83. A method of programming a reference cell in a device, comprising the step of:

programming a threshold voltage of said reference cell utilizing internal circuitry of the device, wherein said step of programming a threshold level includes the step of;

applying array cell to reference cell comparison circuitry to determine a program level of said at least one reference cell.

84. A method of programming a reference cell in a device, comprising the step of:

programming a threshold voltage of said reference cell utilizing internal circuitry of the device, wherein said step of programming a threshold level includes the steps of;

programming said reference cells utilizing control circuitry of said internal circuitry; and

evaluating a programmed state of at least one of said reference cells by comparing the programmed state against a predetermined reference level.

85. The method according to claim 84, wherein said step of evaluating includes the steps of:

applying array cell evaluation voltages to a selected array cell;

applying reference cell evaluation voltages to a reference cell to be evaluated; and

calculating a programmed state of the reference cell to be evaluated using at least one of said array cell evaluation voltages, said reference cell evaluation voltages, and currents flowing through each of said selected array cell and the reference cell to be evaluated to determine a programmed state of said reference cell.

86. The method according to claim 84, wherein said step of evaluating includes the steps of:

adjusting a gate voltage applied to at least one of the reference cells to be evaluated and said selected array cell until a current flowing in each of said selected array cell and the reference cell to be evaluated are equal; and

calculating a programmed state of the reference cell to be evaluated based on a difference in gate voltages between said selected array cell and the reference cell to be evaluated.

87. The method according to claim 84, wherein said step of evaluating includes the steps of:

adjusting a gate voltage applied to at least one of the reference cells to be evaluated and said selected array cell until a ratio of currents flowing in each of said selected array cell and the reference cell to be evaluated comprises a predetermined ratio; and

calculating a programmed state of the reference cell to be evaluated based on a difference in gate voltages between said selected array cell and the reference cell to be evaluated, and said predetermined ratio.

88. The method according to claim 84, wherein said step of evaluating includes the steps of:

applying a source current to a reference cell to be evaluated; and

adjusting a gate voltage the reference cell to be evaluated until one of a stop and start of a predetermined level of current is sourced by the reference cell to be evaluated indicating a programmed state of the reference cell to be evaluated.

89. The method according to claim 85, wherein:

said step of applying array cell evaluation voltages includes at least one step of,

applying at least one external voltage source to said selected array cell,

dividing at least one of an external voltage and an internal voltage source and applying the divided voltage to said selected array cell, and

retrieving a table register value indicating at least one voltage and applying the indicated voltages to said selected array cell; and

said step of applying reference cell evaluation voltages to a reference cell to be evaluated includes at least one step of,

applying at least one external voltage source to the reference cell to be evaluated,

dividing at least one of an external voltage and an internal voltage source and applying the divided voltage to the reference cell to be evaluated, and

retrieving a table register value indicating at least one voltage and applying the indicated voltages to the reference cell to be evaluated.

90. A method of programming a reference cell in a device comprising the steps of:

programming a threshold voltage of said reference cell utilizing internal circuitry of the device;

verifying the programmed threshold of said reference cell; and

repeating said steps of programming and verifying until one of a max number of programming attempts has occurred and a predetermined threshold voltage is attained in said reference cell.

91. A method of programming a reference cell in a device, comprising the step of:

programming a threshold voltage of said reference cell utilizing internal circuitry of the device, wherein said step of programming a threshold voltage comprises the steps of,

determining if said threshold voltage has at least attained a predetermined program level via a program verify operation;

if said threshold voltage has not attained said predetermined programmed level, then performing the step of,

programming the reference cell; and

repeating said steps of determining and programming until at least one of a max number of program attempts occurs and said predetermined program level is attained in said reference cell.

92. The method according to claim 91, further comprising the step of:

verifying the programmed threshold of said reference cell.

93. A memory device, comprising:

at least one array cell configured to store data;

at least one reference cell configured to provide a reference for operations performed on said array cells;

means for performing said operations on said array cells utilizing said reference cells; and

means for programming said reference cells utilizing internal circuitry of said memory device.

94. The memory device according to claim 93, wherein said memory device is a flash memory device.

95. A memory device comprising:

at least one array cell configured to store data;

at least one reference cell configured to provide a reference for operations performed on said array cells;

means for performing said operations on said array cells utilizing said reference cells; and

means for programming said reference cells utilizing internal circuitry of said memory device, wherein said means for programming includes;

means for determining a threshold voltage (V_T) of a selected reference cell by comparing the selected reference cell to a selected array cell; and

means for programming the selected reference cell to a selected V_T based on the determined threshold voltage (V_T).

96. A memory device comprising:

at least one array cell configured to store data;

at least one reference cell configured to provide a reference for operations performed on said array cells;

means for performing said operations on said array cells utilizing said reference cells; and

means for programming said reference cells utilizing internal circuitry of said memory device, wherein said means for programming comprises;

means for producing high level voltages, internal to said device and controlled by said means for performing, for applying programming pulses to said reference cell arrays.