METHOD, APPARATUS, AND SYSTEM FOR IMPROVED ERASE OPERATION IN FLASH MEMORY
First Claim
1. A method comprising:
- erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells of the string of memory cells has a second voltage, the plurality of intermediate memory cells being located between the first memory cell and the second memory cell.
2 Assignments
0 Petitions
Accused Products
Abstract
Various embodiments include erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells between the first memory cell and the second memory cell has a second voltage. Some embodiments include erase verifying only the first memory cell and second memory cell in a first erase verify operation, and erase verifying the plurality of intermediate memory cells in a second erase verify operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
13 Citations
27 Claims
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1. A method comprising:
erasing at least one memory cell of a string of memory cells of a memory device while a control gate of at least one of a first memory cell and a second memory cell of the string of memory cells has a first voltage and while a control gate of each memory cell of a plurality of intermediate memory cells of the string of memory cells has a second voltage, the plurality of intermediate memory cells being located between the first memory cell and the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a string of memory cells including a first memory cell, a second memory cell, and a plurality of intermediate memory cells coupled between the first memory cell and the second memory cell; and a circuit to erase at least one memory cell of the string of memory cells while a first control gate of at least one of the first and second memory cells has a first voltage and while a second control gate of each memory cell of the plurality of intermediate memory cells has a second voltage. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A system comprising:
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a flash memory device including a string of memory cells with a first memory cell, a second memory cell, and plurality of intermediate memory cells coupled between the first memory cell and the second memory cell, and a circuit to erase at least one memory cell of the string of memory cells of a memory device while a first control gate of at least one of the first and second memory cells has a first voltage and while a second control gate of each memory cell of the plurality of intermediate memory cells has a second voltage; and a circuit board coupled to the flash memory device, the circuit board including a terminal to couple to a battery to provide a voltage to the flash memory device. - View Dependent Claims (26, 27)
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Specification