PROGRESSIVE MEMORY INITIALIZATION WITH WAITPOINTS

• US 20080159059A1
• Filed: 01/03/2007
• Published: 07/03/2008
• Est. Priority Date: 01/03/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C.
• Granted Patent: US 8,725,975 B2
• Time in Patent Office: Days
• US Class Current: 365/236
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.

Claims

1. A method comprising:

initializing a counter value of a hardware counter in response to an initialization stimulus;

iteratively adjusting the counter value and storing an initialization value to a memory location of a memory array using a memory address based on the counter value; and

generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting the counter value and storing the initialization value.

2. The method of claim 1, wherein the initialization stimulus is selected from a group consisting of:

a reset stimulus; and

a power-on stimulus.

3. The method of claim 1, wherein:

initializing the counter value of the hardware counter comprises setting the counter value to a non-zero number; and

adjusting the counter value comprises decrementing the counter value.

4. The method of claim 1, further comprising:

executing, with a data processor, a store instruction so as to configure the waitpoint value.

5. The method of claim 1, further comprising:

determining, with a data processor, a progress of an initialization of the memory array based on the counter value.

6. The method of claim 1, further comprising:

suspending an execution of a software program by a data processor prior to the generation of the interrupt request; and

resuming the execution of the software program in response to the generation of the interrupt request.

7. The method of claim 6, further comprising:

replacing the waitpoint value with another waitpoint value in response to resuming the execution of the software program.

8. The method of claim 1, wherein generating the interrupt request comprises:

generating the interrupt request in response to determining that the counter value is equal to the waitpoint value.

9. The method of claim 8, further comprising:

accessing the counter value from the hardware counter;

accessing the waitpoint value from a register; and

comparing the counter value to the waitpoint value to determine whether the counter value has become equal to the waitpoint value.

10. The method of claim 1, wherein storing an initialization value to a memory location comprises storing the initialization value to a data location and an error correcting code location of the memory location.

11. A system comprising:

a memory device comprising;

a memory array comprising a plurality of memory locations;

an initialization module comprising;

a counter;

a first register configured to store a first waitpoint value;

write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter; and

interrupt logic configured to generate a first interrupt request based on a comparison of the counter value of the counter to the first waitpoint value.

12. The system of claim 11, wherein the memory device further comprises:

address generation logic configured to generate the memory address based on the counter value of the counter.

13. The system of claim 11, wherein the memory device further comprises:

a register configured to store the initialization value.

14. The system of claim 11, further comprising:

an error detect/correct module configured to perform an error correction process using data and error correcting code information from an accessed memory location of the memory array.

15. The system of claim 11, further comprising:

a bus coupled to the memory device; and

a processor coupled to the bus and configured to receive the first interrupt request.

16. The system of claim 15, wherein the processor is configured to resume a suspended execution of a software program in response to receiving the first interrupt request.

17. The system of claim 15, wherein the processor is configured to determine a progress of an initialization of the memory device based on the counter value.

18. The system of claim 11, further comprising:

a second register configured to store a second waitpoint value; and

wherein the interrupt logic is configured to generate a second interrupt request based on a comparison of the counter value to the second waitpoint value.

19. The system of claim 11, wherein the interrupt logic is configured to generate the first interrupt request in response to determining that the counter value is equal to the first waitpoint value.

20. In a system comprising a processor, a memory array, a hardware counter, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address based on a counter value of the hardware counter, a register, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the hardware counter to a waitpoint value stored in the register, a computer-readable medium embodying a set of executable instructions, the set of executable instructions including at least one executable instruction configured to manipulate the processor to:

store a waitpoint value at the register;

suspend an execution of the set of executable instructions to wait for an interrupt request from the interrupt logic based on the waitpoint value; and

resume the execution of the set of executable instructions in response to the interrupt request from the interrupt logic.