METHODS OF FABRICATING SHIELD PLATES FOR REDUCED FIELD COUPLING IN NONVOLATILE MEMORY

• US 20080160680A1
• Filed: 12/28/2006
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Yuan, Jack H.
• Application Number:
  US11/617,593
• Publication Number:
  US 20080160680A1
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.

Claims

1. A method of fabricating nonvolatile memory, comprising:

forming a plurality of adjacent charge storage regions in a first direction along a substrate, said charge storage regions having a lower surface level;

forming a plurality of adjacent control gates above said charge storage regions, said control gates having an upper surface level;

forming insulating members along sides of said charge storage regions facing adjacent charge storage regions in said first direction and along sides of said control gates facing adjacent control gates in said first direction, said insulating members extending from at least said lower surface level of said floating gates to at least said upper surface level of said control gates; and

forming conductive isolating members along said insulating members, said isolating members insulated from said charge storage regions and said control gates by said insulating members.

2. The method of claim 1, wherein said conductive isolating members are floating.

3. The method of claim 1, wherein:

each charge storage region of said plurality is part of an individual row of charge storage regions extending in a second direction substantially perpendicular to said first direction;

each isolating member extends along and provides shielding for a row of charge storage regions to which it is closest in said first direction;

said forming a plurality of adjacent control gates includes forming a plurality of world lines extending in said second direction, wherein each word line is formed above a corresponding row of charge storage regions extending in said second direction; and

said method further comprises providing an electrical connection between each isolating member and a word line formed above said row of charge storage regions to which said each isolating member is closest in said first direction.

4. The method of claim 3, wherein:

each word line is formed from a corresponding row of control gates in said second direction.

5. The method of claim 3, wherein:

forming a plurality of word lines includes forming each word line above a corresponding row of control gates in said second direction and providing an electrical connection between said each word line and its corresponding row of control gates.

6. The method of claim 3, wherein:

said electrical connection is provided at a portion of said word line between row control circuitry for said word line and a first charge storage region of said corresponding row of charge storage regions for said word line.

7. The method of claim 3, wherein:

said electrical connection is provided at a portion of said word line that extends beyond a last charge storage region of said corresponding row of charge storage regions for said word line, said last charge storage region is a charge storage region farthest from row control circuitry for said word line

8. The method of claim 3, wherein:

said nonvolatile memory includes a first plurality of bit lines having substantially equally spacing therebetween and a second plurality of bit lines having substantially equal spacing therebetween;

a last bit line of said first plurality of bit lines is adjacent to a first bit line of said second plurality of bit lines, said last bit line and said first bit line have a larger spacing therebetween than said substantially equal spacing between bit lines of said first plurality and bit lines of said second plurality; and

said electrical connection is provided at said larger spacing between said last bit line of said first plurality and said first bit line of said second plurality.

9. The method of claim 1, wherein said isolating members shield said adjacent charge storage regions from electrical field coupling based on charge stored in said adjacent charge storage regions.

10. The method of claim 9, wherein said isolating members shield said adjacent charge storage regions to reduce shifts in the apparent threshold voltages of storage elements formed from said charge storage regions and control gates.

11. The method of claim 1, wherein each conductive isolating member is capacitively coupled to its most adjacent charge storage region and control gate, thereby increasing a coupling ratio between said adjacent charge storage region and said adjacent control gate.

12. The method of claim 1, wherein:

said first direction corresponds to a bit line axis for a NAND string of flash memory devices formed from said plurality of charge storage regions and said plurality of control gates;

said forming insulating members comprises, for each pair of charge storage regions and control gates adjacent in said first direction, forming a first insulating member along a first bit line side of a first charge storage region of said pair and a first bit line side of a first control gate of said pair, and forming a second insulating member along a first bit line side of a second charge storage region of said pair and a first bit line side of a second control gate of said pair; and

said forming conductive isolating members comprises, for said each pair, forming a first isolating member along said first insulating member and a second isolating member along said second insulating member.

13. The method of claim 1, wherein:

said plurality of adjacent charge storage regions includes a first charge storage region adjacent a first select gate for said plurality and a last charge storage region adjacent a second select gate for said plurality;

said forming insulating members includes forming an insulating member along a side of said first charge storage region adjacent to said first select gate in said first direction and forming an insulating member along a side of said last charge storage region adjacent to said second select gate in said first direction; and

said forming conductive isolating members includes forming a first isolating member along said insulating member for said first charge storage region and forming a second isolating member along said insulating member for said last charge storage region.

14. The method of claim 1, wherein:

said first direction corresponds to a bit line axis for a NAND string of flash memory devices formed from said plurality of charge storage regions and said plurality of control gates;

said forming insulating members comprises, for each pair of charge storage regions and control gates adjacent in said first direction, forming a first insulating member along a first bit line side of a first charge storage region of said pair and a first bit line side of a first control gate of said pair, and forming a second insulating member along a first bit line side of a second charge storage region of said pair and a first bit line side of a second control gate of said pair; and

said forming conductive isolating members comprises, for said each pair, forming a single isolating member between said first insulating member and said second insulating member.

15. The method of claim 1, wherein forming a plurality of adjacent control gates consists of forming a plurality of word lines.

16. The method of claim 1, further comprising:

forming a plurality of adjacent word lines above said plurality of adjacent control gates, wherein each individual word line is connected to an individual one of said adjacent control gates.

17. The method of claim 1, wherein:

forming said conductive isolating members comprises depositing polysilicon.

18. The method of claim 17, wherein depositing polysilicon comprises depositing and etching said polysilicon to form isolating sidewalls having a thickness less than 50 angstroms.

19. The method of claim 1, wherein:

forming said insulating members comprises depositing at least one layer of oxide or nitride.

20. The method of claim 1, wherein:

forming said insulating members comprises depositing insulating sidewalls along said sides of said charge storage regions and control gates.

21. The method of claim 1, further comprising:

forming a dielectric layer above said substrate prior to forming said plurality of charge storage regions, said charge storage regions are formed above said dielectric layer.

22. The method of claim 1, wherein:

said control gates consist of one or more layers of a conductive material.

23. The method of claim 1, wherein:

said charge storage regions are conductive floating gate regions.

24. The method of claim 1, wherein:

said charge storage regions are dielectric charge storage regions.

25. The method of claim 1, wherein:

said charge storage regions are tailored dielectric layers.

26. The method of claim 1, wherein:

said plurality of charge storage regions and said plurality of control gates form storage elements for a NAND string.

27. The method of claim 26, wherein forming said plurality of charge storage regions and control gates is performed while fabricating an array of NAND flash memory devices.

28. The method of claim 1, wherein said plurality of charge storage regions and said plurality of control gates form multi-state flash memory devices.

29. A method of fabricating nonvolatile memory, comprising:

forming a plurality of charge storage regions above a substrate, said charge storage regions having two substantially parallel sides in a bit line direction;

forming a plurality of control gates above said charge storage regions;

forming first and second insulating layers between said bit line sides of charge storage regions adjacent in said bit line direction; and

forming at least one floating isolation shield between each of said first and second insulating layers.

30. The method of claim 29, wherein forming said at least one floating isolation shield between each of said first and second insulating layers includes depositing polysilicon to form a first isolating sidewall along each of said first insulating layers and a second isolating sidewall along each of said second insulating layers.

31. The method of claim 30, wherein forming first and second insulating layers includes forming each of said first and second insulating layers between bit line sides of control gates adjacent in said bit line direction, said bit line sides of said control gates are substantially co-planar with bit line sides of corresponding ones of said charge storage regions, said insulating layers extending from a lower surface level of said control gates to an upper surface level of said control gates.

32. The method of claim 31, wherein:

each of said first isolating sidewalls shields an adjacent charge storage region located across a corresponding first insulating layer; and

each of said second isolating sidewalls shields an adjacent charge storage region located across a corresponding second insulating layer.

33. The method of claim 32, wherein said first and second isolating sidewalls are capacitively coupled across said first and second insulating layers to corresponding ones of said control gates and corresponding ones of said charge storage regions, thereby increasing a coupling ratio between each of said control gates and a corresponding charge storage region.

34. The method of claim 29, wherein forming said at least one floating isolation shield between each of said first and second insulating layers comprises forming a single isolation shield between each of said first and second insulating layers.

35. The method of claim 29, wherein forming each of said at least one floating isolation shields includes forming insulation around substantially all of said at least one floating isolation shield such that no electrical connection is provided to said at least one floating isolation shield.

36. The method of claim 29, wherein:

forming said plurality of control gates includes forming a plurality of word lines extending in a word line direction substantially perpendicular to said bit line direction;

forming each of said first and second insulating layers includes forming said first insulating layer along a bit line side of a first word line and forming said second insulating member along a bit line side of a second word line adjacent to said first word line; and

forming said at least one floating isolation shield includes forming a first isolating sidewall extending in said word line direction along said first insulating layer and forming a second isolating sidewall extending in said word line direction along said second insulating layer.

37. The method of claim 29, wherein:

said plurality of charge storage regions form a NAND string of nonvolatile storage elements; and

said NAND string is electrically connected with a plurality of additional NAND strings to form an array of flash storage devices.

38. The method of claim 29, wherein:

said plurality of charge storage regions form a plurality of multi-state flash storage devices.

39. A method of fabricating nonvolatile memory, comprising:

forming charge storage regions above a substrate, said charge storage regions having two substantially parallel sides in a bit line direction;

forming control gates above said charge storage regions, said control gates having two substantially parallel sides in said bit line direction, each of said control gates is associated with an individual word line extending in a word line direction substantially perpendicular to said bit line direction;

forming insulation layers along said bit line sides of said charge storage regions;

forming said insulation layers along said bit lines sides of said control gates;

forming conductive isolation shields along said insulation layers, said isolation shields insulated from said charge storage regions and said control gates by said insulation layers; and

providing an electrical connection for each word line to one or more of said isolation shields adjacent to a charge storage region associated with said each word line.

40. The method of claim 39, wherein:

said charge storage regions are arranged in rows extending in said word line direction;

said conductive isolation shields include first and second isolation shields adjacent to each row of charge storage regions and on opposite sides thereof in said bit line direction; and

said electrical connection for each word line includes an electrical connection to said first and second conductive isolation shields adjacent to each row.

41. The method of claim 39, wherein:

said electrical connection for each word line is provided at a portion of said word line extending beyond a last charge storage region associated with said word line.

42. The method of claim 39, wherein:

said nonvolatile memory includes a first plurality of bit lines having substantially equally spacing therebetween and a second plurality of bit lines having substantially equal spacing therebetween;

a last bit line of said first plurality of bit lines is adjacent to a first bit line of said second plurality of bit lines, said last bit line and said first bit line have a larger spacing therebetween than said substantially equal spacing between bit lines of said first plurality and bit lines of said second plurality; and

said electrical connection for each word line is provided at said larger spacing between said last bit of said first plurality and said first bit line of said second plurality.

43. The method of claim 39, wherein:

said control gates are word lines.

44. The method of claim 39, wherein:

said charge storage regions form a plurality of multi-state flash storage devices.

45. The method of claim 39, wherein:

said charge storage regions form an array of NAND flash memory devices.