METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING CHANNEL LAYERS HAVING IMPROVED DEFECT DENSITY AND SURFACE ROUGHNESS CHARACTERISTICS

• US 20080160726A1
• Filed: 12/21/2007
• Published: 07/03/2008
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Bo-Un, Hong, Chang-Ki, Choi, Suk-Hun, Han, Sang-Yeob, Yun, Seong-Kyu, Lim, Jong Heun
• Granted Patent: US 7,678,625 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.

Claims

1. A method of fabricating a semiconductor device including a channel layer, the method comprising:

forming a single crystalline silicon layer on a single crystalline silicon substrate, the single crystalline silicon layer having a protrusion extending from a surface thereof;

forming a sacrificial layer on the single crystalline silicon layer;

removing a portion of the sacrificial layer and a portion of the protrusion of the single crystalline silicon layer in a first polishing process to define a sacrificial layer pattern and a remaining portion of the protrusion;

removing the sacrificial layer pattern; and

then

planarizing the surface of the single crystalline silicon layer in a second polishing process to remove the remaining portion of the protrusion and define a substantially planar silicon channel layer.

2. The method of claim 1, prior to forming the single crystalline silicon layer, further comprising:

forming an insulating interlayer having an opening extending therethrough on the single crystalline silicon substrate, the opening exposing a surface of the single crystalline silicon substrate; and

forming a single crystalline silicon pattern on the exposed surface of the single crystalline silicon substrate to fill the opening.

3. The method of claim 2, wherein forming the single crystalline silicon pattern comprises:

performing a selective epitaxial growth (SEG) process using the exposed surface of the single crystalline silicon substrate as a seed.

4. The method of claim 2, wherein forming the single crystalline silicon layer comprises:

forming an amorphous silicon layer on the insulating interlayer and the single crystalline silicon pattern; and

crystallizing the amorphous silicon layer to form the single crystalline silicon layer using the single crystalline silicon pattern as a seed.

5. The method of claim 4, wherein the amorphous silicon layer is formed to a thickness of about 500 Å

to about 5000 Å

.

6. The method of claim 4, wherein crystallizing the amorphous silicon layer comprises:

scanning a laser beam onto the amorphous silicon layer.

7. The method of claim 1, wherein the sacrificial layer is formed to a thickness of about 10 Å

to about 1000 Å

.

8. The method of claim 1, wherein the sacrificial layer comprises silicon oxide and/or silicon nitride.

9. The method of claim 1, wherein the first polishing process is performed using a slurry having a higher polishing rate with respect to the single crystalline silicon layer than the sacrificial layer.

10. The method of claim 9, wherein sacrificial layer comprises silicon oxide, and wherein the first polishing process is performed using a slurry comprising about 0.5% to about 20% by weight of a silica abrasive, about 0.001% to about 1.0% by weight of an amine compound, and/or about 0.001% to about 1.0% by weight of a surfactant and water, the slurry having a pH from about 8 to about 12.

11. The method of claim 1, wherein the first polishing process is performed until the remaining portion of the protrusion of the single crystalline silicon layer comprises about 5% to about 50% of an initial height of the protrusion.

12. The method of claim 1, wherein the second polishing process is performed until the silicon channel layer has a surface roughness RMS of about 0.5 Å

to about 5 Å

.

13. The method of claim 1, wherein removing the sacrificial layer pattern is performed by a wet etching process.

14. A method of manufacturing a semiconductor device, the method comprising:

forming an insulating interlayer having an opening extending therethrough on a single crystalline silicon substrate, the opening exposing a surface of the single crystalline silicon substrate;

forming a single crystalline silicon pattern on the exposed surface of the single crystalline silicon substrate to fill the opening;

forming a single crystalline silicon layer on the insulating interlayer and the single crystalline silicon pattern, the single crystalline silicon layer having a protrusion extending from a surface thereof;

forming a sacrificial layer on the single crystalline silicon layer;

removing a portion of the sacrificial layer and a portion of the protrusion of the single crystalline silicon layer in a first polishing process to define a sacrificial layer pattern and a remaining portion of the protrusion;

removing the sacrificial layer pattern;

planarizing the surface of the second single crystalline silicon layer in a second polishing process to remove the remaining portion of the protrusion and define a substantially planar silicon channel layer; and

forming a transistor on the silicon channel layer.

15. The method of claim 14, further comprising:

forming a second transistor on the single crystalline silicon substrate prior to forming the insulating interlayer thereon.

16. The method of claim 14, wherein the first polishing process is performed using a slurry having a higher polishing rate with respect to the single crystalline silicon layer than the sacrificial layer.

17. The method of claim 14, wherein the first polishing process is performed until the remaining portion of the protrusion of the single crystalline silicon layer comprises about 5% to about 50% of an initial height of the protrusion.

18. The method of claim 14, wherein the second polishing process is performed until the silicon channel layer has a surface roughness RMS of about 0.5 Å

to about 5 Å

.

19. A method of fabricating a semiconductor device, the method comprising:

forming a single crystalline semiconductor layer on a semiconductor substrate, the single crystalline semiconductor layer having a protrusion extending from a surface thereof;

performing a first polishing process on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion; and

performing a second polishing process that is different from the first polishing process to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness.

20. The method of claim 19, wherein performing the first polishing process comprises:

forming a sacrificial layer on the single crystalline semiconductor layer;

performing the first polishing process using the sacrificial layer as a polish stop to remove a majority of the protrusion and define a sacrificial layer pattern on the surface of the single crystalline semiconductor layer adjacent the remaining portion of the protrusion; and

removing the sacrificial layer pattern prior to performing the second polishing process.