METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CONCURRENT MODEL AIDED ELECTRONIC DESIGN AUTOMATION

• US 20080162103A1
• Filed: 10/02/2007
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Abandoned Application

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., White, David
• Application Number:
  US11/866,378
• Publication Number:
  US 20080162103A1
• Time in Patent Office: Days
• US Class Current: 703/13
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness

Abstract

Disclosed are improved methods, systems, and computer program products for predicting performance, manufacturability, and reliability (PMR) using concurrent model analyses for electronic designs. Various embodiments of the present invention disclose a method for predicting PMR with concurrent process model analysis in which a method with concurrent model(s) generate a design for the one or more layers in the electronic circuit. The method then analyzes the impact of the processes or techniques for feature geometric characteristic predictions or PMR evaluations, based upon the concurrent models. Results may be reported to the users, or the method may modify the designs to accommodate the variations and determines one or more parameters based upon the concurrent models. One embodiment determines the impact of concurrent model on one or more of performance, manufacturability, and reliability criteria.

Claims

1. A machine-implemented method for predicting performance, manufacturability, or reliability (PMR) with concurrent model analysis, comprising:

identifying an electronic circuit design for an electronic circuit to be manufactured by a first manufacturing process;

identifying a first concurrent model of the first manufacturing process for a first level of the electronic circuit;

determining a first geometric characteristic of a first feature of the first level based upon the first concurrent model;

determining a first metric of the first level based upon the first geometric characteristic of the first feature of the first level;

determining whether a first PMR requirement is satisfied for the electronic circuit based upon the first geometric characteristic or the first metric; and

displaying the first geometric characteristic of the first level or storing the first geometric characteristic in a tangible computer accessible medium.

2. The machine-implemented method of claim 1, in which the first manufacturing process comprises a fabrication process or technique, a metrology process or technique, or an image processing process or technique.

3. The machine-implemented method of claim 1, in which the first geometric characteristic comprises a dimension or a profile of the first feature.

4. The machine-implemented method of claim 1, further comprising:

determining whether there is a second level of the electronic circuit.

5. The machine-implemented method of claim 4, in which the second level of the electronic circuit is determined to exist, further comprising:

forwarding the first geometric characteristic or the first metric to the second level for analysis.

6. The machine-implemented method of claim 4, in which the second level of the electronic circuit is determined to exist, further comprising:

identifying a second concurrent model of a second manufacturing process for the second level of the electronic circuit;

determining a second geometric characteristic of a second feature of the second level based upon the second concurrent model; and

determining a second metric of the second level based upon the second geometric characteristic of the second feature.

7. The machine-implemented method of claim 6, further comprising:

determining whether a second PMR requirement is satisfied for the second level based upon the second characteristic or the second metric.

8. The machine-implemented method of claim 6, further comprising:

determining whether a third PMR requirement is satisfied for the electronic circuit based upon the first geometric characteristic, the first metric, the second geometric characteristic, or the second metric.

9. The machine-implemented method of claim 4, further comprising:

determining whether a third PMR requirement is satisfied for the first and the second level combined.

10. The machine-implemented method of claim 1, in which the first metric comprises an electrical, physical, chemical, or thermal characteristic related to the first level of the electronic circuit.

11. The machine-implemented method of claim 5, in which the electrical characteristic comprises electrical resistivity, capacitance, inductance, or a derivative electrical characteristic of a feature on the first level of the electronic circuit.

12. The machine-implemented method of claim 6, in which the derivative electrical characteristic is determined based upon one or more of the electrical resistivity or capacitance and may comprise electrical resistance, current density, IR drop, power consumption, RC time constant, or capacitive load of the feature on the first level of the electronic circuit.

13. The machine-implemented method of claim 5, in which the physical characteristic related to the first level of the electronic circuit comprises uniformity of a feature across the first level of the electronic circuit design, uniformity of the feature from a first die to a second die, or uniformity of the feature from a first wafer to a second wafer.

14. The machine-implemented method of claim 5, in which the chemical characteristic related to the first level of the electronic circuit comprises a composition, bulk density, or distribution of a feature on the first level of the electronic circuit.

15. The machine-implemented method of claim 1, in which the first or the second PMR requirement comprises a performance requirement, a manufacturability requirement, or a reliability requirement.

16. The machine-implemented method of claim 1, in which the performance requirement comprises a timing requirement or a power consumption requirement.

17. The machine-implemented method of claim 8, in which the first concurrent model is substantially similar to the second concurrent model.

18. The machine-implemented method of claim 7, in which the first manufacturing process is substantially similar to the second manufacturing process.

19. The machine-implemented method of claim 7, comprising:

calibrating the first concurrent model or the second concurrent model with information obtained from a patterned test wafer or from a source with limited fidelity.

20. The machine-implemented method of claim 7, in which the identifying a first concurrent model or the identifying a second concurrent model comprises directly modeling underlying physics of the manufacturing process, modeling underlying physics in conjunction with the information obtained from a patterned test wafer or a source of limited fidelity, or constructing rules based upon the information obtained from a patterned test wafer or a source of limited fidelity.

21. The machine-implemented method of claim 1, further comprising:

combining the concurrent model with additional measured or model produced statistical variability to produce a distribution of values related to the first geometric characteristic.

22. The machine-implemented method of claim 1, in which a portion of the layout is generated by a context simulation method.

23. A system for predicting performance, manufacturability, or reliability (PMR) with concurrent model analysis, comprising:

means for identifying an electronic circuit design for an electronic circuit to be manufactured by a first manufacturing process;

means for identifying a first concurrent model of the first manufacturing process for a first level of the electronic circuit;

means for determining a first geometric characteristic of a first feature of the first level based upon the first concurrent model;

means for determining a first metric of the first level based upon the first geometric characteristic of the first feature of the first level;

means for determining whether a first PMR requirement is satisfied for the electronic circuit based upon the first geometric characteristic or the first metric; and

means for displaying the first geometric characteristic of the first level or storing the first geometric characteristic in a tangible computer accessible medium.

24. A computer program product comprising a computer-usable storage medium having executable code to execute a process for predicting performance, manufacturability, or reliability (PMR) with concurrent model analysis, comprising:

identifying an electronic circuit design for an electronic circuit to be manufactured by a first manufacturing process;

identifying a first concurrent model of the first manufacturing process for a first level of the electronic circuit;

determining a first geometric characteristic of a first feature of the first level based upon the first concurrent model;

determining a first metric of the first level based upon the first geometric characteristic of the first feature of the first level;

determining whether a first PMR requirement is satisfied for the electronic circuit based upon the first geometric characteristic or the first metric; and

displaying the first geometric characteristic of the first level or storing the first geometric characteristic in a tangible computer accessible medium.