Multi buffer asynchronous scheme for processing incoming information

• US 20080162751A1
• Filed: 01/03/2007
• Published: 07/03/2008
• Est. Priority Date: 01/03/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wilson, Thomas James
• Granted Patent: US 8,489,783 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Claims

1. A method for processing incoming data by an incoming data module and a processor, the method comprising:

waiting until two flags have identical values by the incoming data module;

when the two flags do have identical values, selecting one of two buffers depending on the values of the flags by the incoming data module;

saving a set of data into the selected buffer by the incoming data module;

changing a first flag of the two flags by the incoming data module;

alerting the processor by the incoming data module;

identifying the selected buffer by the processor; and

processing the data of the selected buffer by the processor.

2. The method of claim 1, further comprising the steps of:

receiving a plurality of incoming analog data by the incoming data module; and

digitizing the plurality of incoming analog data into a set of digital data,

wherein the set of digital data is the set of data saved in the selected buffer.

3. The method of claim 2, further comprising the step of stopping the generation of incoming analog data, said stopping being caused by the incoming data module in the event that the flags do not have identical values.

4. The method of claim 3, wherein the causing the stopping of generation of incoming analog data is performed by stopping the generation of one or more stimulation signals.

5. The method of claim 1, further comprising changing the second flag by the processor.

6. The method of claim 5, wherein the step of changing the second flag by the processor is performed after all data in the other of the two buffers has been processed.

7. The method of claim 1, wherein the incoming data module and the processor operate in parallel.

8. The method of claim 1, wherein the step of saving a set of data into the selected buffer further includes overwriting data previously stored in and processed from the selected buffer.

9. A method for processing incoming data comprising:

waiting until two flags have identical values by an incoming data module;

when the two flags do have identical values, selecting one of two buffers depending on the values of the flags by the incoming data module;

saving a set of data into the selected buffer by the incoming data module;

changing a first flag of the two flags by the incoming data module; and

alerting a processor by the incoming data module.

10. The method of claim 9, further comprising the steps of:

receiving the alert by the processor;

changing the second flag by the processor if all data in the other one of the two buffers has been processed;

identifying the selected buffer by the processor; and

processing the data of the selected buffer by the processor.

11. The method of claim 10 further comprising:

repeatedly performing the enumerated steps by the incoming data module and the processor for a plurality of incoming sets of data, wherein the processing the data of the selected buffer by the processor is performed for a first set of data while the incoming data module performs the saving a set of data step for a second set of data.

12. The method of claim 10, wherein the incoming data module and the processor operate in parallel.

13. The method of claim 10, wherein the step of saving a set of data into the selected buffer further includes overwriting data previously stored in and processed from the selected buffer.

14. A method for processing data by an incoming data module and a processor comprising:

consulting one or more flags by the incoming data module to select a first buffer from a plurality of buffers, the first buffer being available to store information into;

storing a first set of information into the first buffer by the incoming data module;

modifying the one or more flags to indicate that new information has been stored in the first buffer by the incoming data module;

processing the information in the first buffer by the processor; and

modifying the one or more flags by the processor to indicate that the first buffer is available to store information into,

wherein the processor and the incoming data module operate in parallel.

15. The method of claim 14, wherein the incoming data module is storing a second set of data into a second buffer, while the processor processes the first set of data in the first buffer.

16. A method for processing data by a plurality of incoming data modules and a plurality of processors comprising:

consulting one or more flags by the plurality of incoming data modules so that each incoming data module selects a buffer from a plurality of buffers, the selected buffer being available to store information into;

changing the one or more flags by each incoming data module to indicate that each respective selected buffer is being used;

storing a respective set of information into each selected buffer by the plurality of incoming data modules;

modifying the one or more flags to indicate that new information has been stored in each selected buffer by the plurality of incoming data modules;

processing the information in a plurality of buffers in which new information has been stored by the plurality of processors; and

modifying the one or more flags by each of the processors to indicate that the respective buffers are available to store information into,

wherein the plurality of processors and the plurality of incoming data modules operate in parallel.

17. A system for processing incoming information comprising:

a source of incoming data;

an incoming data module connected to the source of incoming data;

a processor connected to the incoming data module;

a memory comprising two buffers and connected to the processor and the source of incoming data; and

two flags accessible by the processor and the source of incoming data;

wherein the incoming data module is configured to

wait until the two flags have identical values, and when the two flags do have identical values, select one of two buffers depending on the values of the flags, save a set of data received from the source of incoming data into the selected buffer, change a first flag of the two flags, and alert the processor,

and the processor is configured to

receive the alert, change the second flag if all data in the other one of the two buffers has been processed, identify the selected buffer, and process the data of the selected buffer.

18. The system of claim 17, wherein the processor and the incoming data module operate in parallel.

19. The system of claim 17, wherein the memory further comprises instructions, which are executed by the processor in order to perform its associated steps.

20. The system of claim 17, wherein the incoming data module further comprises application specific logic which performs its associated steps.

21. The system of claim 17 wherein the memory is random access memory.

22. The system of claim 17, wherein the memory is a register file.

23. The system of claim 17, further comprising a bus connecting the incoming data module, the memory and the processor.

24. The system of claim 17, wherein the saving a set of data into the selected buffer by the incoming data module further comprises overwriting previously saved and processed data.

25. The system of claim 17 wherein the source of incoming data provides incoming analog data and the incoming data module is further configured to convert the incoming analog data into digital data.

26. A system for processing incoming information comprising:

a source of incoming data;

an incoming data module connected to the source of incoming data;

a processor connected to the incoming data module;

a memory comprising two buffers and connected to the processor and the source of incoming data; and

two flags accessible by the processor and the source of incoming data;

wherein the incoming data module is configured to wait until two flags have identical values and when the two flags do have identical values, select one of two buffers depending on the values of the flags, save a set of data received from the source of incoming data into the selected buffer, change a first flag of the two flags, and alert the processor.

27. The system of claim 26, wherein the processor is configured to:

receive the alert;

change the second flag if all data in the other one of the two buffers has been processed;

identify the selected buffer; and

process the data of the selected buffer.

28. The system of claim 27 wherein the processor and the incoming data module operate in parallel.

29. The system of claim 27, wherein the memory further comprises instructions, which are executed by the processor in order to perform its associated steps and the incoming data module further comprises application specific logic which performs its associated steps.

30. The system of claim 26, wherein the system is a mobile telephone.

31. The system of claim 26, wherein the system is a portable audio player.

32. A system comprising:

a plurality of processors;

a plurality of incoming data modules connected to the plurality of processors; and

a memory comprising a plurality of buffers and one or more flags, the memory being connected to the plurality of processors and the plurality of incoming data modules;

wherein the plurality of processors and the plurality of incoming data modules operate in parallel, each of the plurality of incoming data modules comprises logic configured to;

consult one or more flags in order to select a buffer from a plurality of buffers, which is available to store information into;

change the one or more flags to indicate that the selected buffer is being used;

store a respective set of information into the selected buffer; and

modify the one or more flags to indicate that new information has been stored in the selected buffer,

and the memory further comprises instructions configured to cause each of the plurality of processors to;

consult the one or more flags to locate the selected buffer into which new information has been stored;

process the information in the selected buffer; and

modify the one or more flags to indicate that the respective buffers are available to store information into.

33. A mobile telephone comprising:

a source of incoming data;

an incoming data module connected to the source of incoming data;

a processor connected to the incoming data module;

a memory comprising two buffers and connected to the processor and the source of incoming data; and

two flags accessible by the processor and the source of incoming data;

wherein the incoming data module is configured to

wait until the two flags have identical values, and when the two flags do have identical values, select one of two buffers depending on the values of the flags, save a set of data received from the source of incoming data into the selected buffer, change a first flag of the two flags, and alert the processor,

and the processor is configured to

receive the alert, change the second flag if all data in the other one of the two buffers has been processed, identify the selected buffer, and process the data of the selected buffer.

34. A portable audio player comprising:

a source of incoming data;

an incoming data module connected to the source of incoming data;

a processor connected to the incoming data module;

a memory comprising two buffers and connected to the processor and the source of incoming data; and

two flags accessible by the processor and the source of incoming data;

wherein the incoming data module is configured to

wait until the two flags have identical values, and when the two flags do have identical values, select one of two buffers depending on the values of the flags, save a set of data received from the source of incoming data into the selected buffer, change a first flag of the two flags, and alert the processor,

and the processor is configured to

receive the alert, change the second flag if all data in the other one of the two buffers has been processed, identify the selected buffer, and process the data of the selected buffer.