METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS MEMORY SYSTEM

• US 20080162759A1
• Filed: 02/25/2008
• Published: 07/03/2008
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Sidiropoulos, Stefanos, Stark, Donald C., Portmann, Clemenz, Davis, Paul G., Donnelly, Kevin S., Chau, Pak Shing, Garlepp, Bruno Werner
• Granted Patent: US 8,296,540 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

Claims

1. An integrated circuit, configured as a master device, comprising:

a register to store a value that represents temperature information pertaining to the integrated circuit; and

an adjustment circuit to adjust a clock signal in response to the value that represents temperature information.

2. The integrated circuit of claim 1, wherein:

the integrated circuit further comprises a bus interface; and

wherein the bus interface is adapted to communicate with a data communications bus in response to the adjustment circuit at a rate determined by the clock signal as adjusted by the adjustment circuit.

3. The integrated circuit of claim 2, wherein the data communications bus is an external data communications bus, the master device thereby adapted to control data communications external to the integrated circuit in a manner influenced by the adjustment circuit.

4. The integrated circuit of claim 1, further comprising a temperature sensor internal to the integrated circuit, the register coupled to the temperature sensor, the register adapted to store the value that represents the temperature information sensed by the temperature sensor.

5. The integrated circuit of claim 1, wherein the master device includes a system controller.

6. The integrated circuit of claim 5, wherein the system controller includes a memory system controller.

7. The integrated circuit of claim 1, further comprising an interface to output an adjustment signal, in response to the value that represents the temperature information, to a slave device.

8. The integrated circuit of claim 1, wherein the adjustment circuit is adapted to modify operating frequency of at least one component within the integrated circuit based on the value that represents temperature information.

9. The integrated circuit of claim 1, wherein:

the integrated circuit further comprises a clock recovery and alignment circuit; and

the adjustment circuit is adapted to at least partially control the clock recovery and alignment circuit in response to the value that represents temperature information for adjusting the clock signal.

10. A method comprising:

obtaining information that represents a temperature;

storing the information that represents the temperature into a register; and

adjusting a clock signal in response to the information that represents the temperature to obtain an adjusted clock signal.

11. The method of claim 10, wherein the method is performed in an integrated circuit and the integrated circuit includes an interface adapted to be coupled to an external data path.

12. The method of claim 11, further comprising:

transferring data at the interface in response to the adjusted clock signal.

13. The method of claim 12, wherein the external data path is a data communications bus, wherein the integrated circuit is configured as a master device that transfers the data to an integrated circuit memory device via the data communication bus.

14. The method of claim 10 wherein the obtaining includes measuring the temperature of a circuit component to obtain the information that represents the temperature.

15. The method of claim 14, wherein the measuring is performed by a temperature sensor.

16. The method of claim 10, further comprising generating the clock signal from a clock source.

17. The method of claim 16, further comprising:

transferring write data to be stored in an integrated circuit memory device; and

,

wherein the transferring of the write data is synchronized with the adjusted clock signal.

18. An integrated circuit device, comprising:

a storage circuit to store information representing an operating parameter and information representing an operating frequency; and

an adjustment circuit to adjust a circuit based on the information representing the operating parameter and information representing the operating frequency.

19. The integrated circuit device of claim 18, wherein the information representing the operating parameter includes a power supply parameter.

20. The integrated circuit device of claim 18, wherein the information representing the operating parameter includes information representing temperature.

21. The integrated circuit device of claim 18, further comprising an internal detector circuit to detect the operating parameter.

22. The integrated circuit device of claim 21, wherein the internal detector circuit is a temperature detector.

23. The integrated circuit device of claim 18, embodied as a device, further comprising a receiver to receive the information representing the operating parameter.

24. The integrated circuit device of claim 18, wherein the integrated circuit device is an integrated circuit master device.

25. The integrated circuit device of claim 24, embodied within a memory system including a plurality of integrated circuit memory devices.

26. An integrated circuit device, comprising:

a storage circuit to store information representing a clock parameter and information representing a temperature; and

an adjustment circuit to adjust a circuit based on the information representing the clock parameter and information representing the temperature.

27. The integrated circuit device of claim 26, wherein the clock parameter is selected from at least one of a clock frequency, a clock phase, a clock delay and a slew rate.

28. The integrated circuit of claim 27, wherein the integrated circuit device is a memory controller adapted to output the information representing a clock parameter and the information representing the temperature to at least one integrated circuit memory device.

29. An apparatus, comprising:

a temperature sensor to sense a temperature;

a clock generator to provide a clock signal used for data communications;

a storage circuit to store information representing at least one of the plural operating parameters; and

a clock alignment circuit to adjust the clock signal using at least one operating parameter represented by the information in response to the temperature.

30. The apparatus of claim 29, wherein at least one of the operating parameters is a clock frequency.

31. The apparatus of claim 29, wherein at least one of the operating parameters is a clock phase.

32. The apparatus of claim 29, wherein at least one of the operating parameters is a clock delay.

33. The apparatus of claim 29, wherein at least one of the operating parameters is a slew rate limit.

34. The apparatus of claim 29, further comprising a master device.

35. The apparatus of claim 34, wherein the master device is a memory controller adapted to output the information representing at least one of the plural operating parameters and information representing the temperature to at least one integrated circuit memory device.

36. The apparatus of claim 35, wherein the temperature sensor is external to the integrated circuit memory controller.

37. The apparatus of claim 29, wherein the clock generator receives a master clock signal from an external source and derives the clock signal from the master clock signal.

38. The apparatus of claim 29, wherein the clock alignment circuit is embodied in a master device that includes an integrated circuit memory controller, and the clock signal is provided to an integrated circuit memory device.