HARDWARE VOTING MECHANISM FOR ARBITRATING SCALING OF SHARED VOLTAGE DOMAIN, INTEGRATED CIRCUITS, PROCESSES AND SYSTEMS

• US 20080162770A1
• Filed: 12/11/2007
• Published: 07/03/2008
• Est. Priority Date: 11/01/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Titiano, Patrick C., Qasem, Safwan
• Granted Patent: US 8,327,158 B2
• Time in Patent Office: Days
• US Class Current: 710/309
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage output (VDD1) is coupled to said processors (CPU1, CPU2) and further has a voting circuit (4520) responsive to the voltage requests (Vcpu1, Vcpu2) and operable to automatically establish a function (Fct) of the respective voltage requests (Vcpu1, Vcpu2) to control the controllable supply voltage output (VDD1).

Claims

1. An electronic circuit comprising:

processors operable to make respective voltage requests; and

a power management circuit having a controllable supply voltage output coupled to said processors and further having a voting circuit responsive to the voltage requests and operable to automatically establish a function of the respective voltage requests to control the controllable supply voltage output.

2. The electronic circuit claimed in claim 1 wherein said power management circuit has at least one register, and said processors are operable to send their respective voltage requests as multi-bit voltage magnitude representations to said at least one register.

3. The electronic circuit claimed in claim 1 wherein the electronic circuit has a first voltage domain and a second voltage domain both coupled to said power management circuit, said first voltage domain including said processors, said second voltage domain including additional processors operable to make additional respective voltage requests, and said power management circuit has a second controllable supply voltage output and further has an additional voting circuit responsive to the additional respective voltage requests, said power management circuit operable to automatically establish a function of the additional voltage requests for the second voltage domain to control the second controllable supply voltage output for the second voltage domain.

4. The electronic circuit claimed in claim 1 wherein said processors each have a respective awake/not-awake state, and said power management circuit is responsive to establish the highest of the respective voltage requests of the processors that are in the awake state.

5. The electronic circuit claimed in claim 1 wherein said processors have a sleep mode and said power management circuit is responsive to establish the controllable supply voltage output as a function of the sleep mode when said processors are all in the sleep mode and otherwise as a function of the voltage requests of said processors that are not in the sleep mode.

6. The electronic circuit claimed in claim 1 wherein said power management circuit also controls a clock frequency for said processors.

7. An electronic circuit comprising:

processors operable to output respective voltage requests;

a voltage supply having a controllable voltage supply output coupled to said processors; and

a voting circuit having respective inputs coupled to said processors, said voting circuit having a voltage control output coupled to said voltage supply, said voting circuit operable in response to the respective inputs to automatically scale the controllable voltage supply output from said power supply substantially to the highest of the voltage requests.

8. The electronic circuit claimed in claim 7 wherein said voting circuit has respective register fields for the input from each processor and each said processor is operable to write its respective voltage request into a corresponding said register field.

9. The electronic circuit claimed in claim 7 wherein at least one of said processors is operable to execute a dynamic voltage and frequency scaling (DVFS) power management process to output its voltage request to said voting circuit.

10. The electronic circuit claimed in claim 7 wherein said processors have a respective interrupt input, and said voting circuit inputs are independent from each such interrupt input.

11. The electronic circuit claimed in claim 7 wherein said processors are operable for inter-processor communication, and said voting circuit controls said voltage control output separate from inter-processor communication.

12. The electronic circuit claimed in claim 7 wherein said voting circuit is responsive to any awake processor among said processors independently of any not-awake processor among said processors.

13. The electronic circuit claimed in claim 7 wherein said processors have a control for an awake and not-awake state, and said voting circuit inputs include a first input from a first processor among said processors and a second input from a second processor among said processors, and said first input is isolated from said control for awake and not-awake state of said second processor, and said voting circuit second input is isolated from said control for awake and not-awake state of said first processor.

14. The electronic circuit claimed in claim 7 wherein at least two of said processors have a different architecture from each other.

15. An electronic circuit comprising:

a set of processors that use a shared resource for operation of said set of processors, the shared resource having a plurality of resource levels;

a set of shared resource control registers coupled to said set of processors, at least two of said shared resource control registers operable to store respective multi-bit values representing respectively requested levels among the plurality of resource levels, said processors each operable to supply a respective multi-bit value to at least one of the corresponding shared resource control registers; and

an arbitrating circuit coupled to said shared resource control registers and responsive to output a multi-bit value representing an arbitrated resource level of the shared resource.

16. The electronic circuit claimed in claim 15 further comprising a scalable resource controller responsive to said arbitrating circuit to deliver the shared resource to the set of processors at substantially the arbitrated resource level of the shared resource represented by the multi-bit value output from said arbitrating circuit.

17. The electronic circuit claimed in claim 16 further comprising a serial communication circuit coupling said arbitrating circuit to said scalable resource controller.

18. The electronic circuit claimed in claim 15, further comprising an address decoder coupled to said set of processors, said processors each operable to supply a respective address to said address decoder, said address decoder operable to select said at least one of the corresponding shared resource control registers in response to the respective address so that the respective multi-bit value from a given said processor is stored to said at least one of the corresponding shared resource control registers.

19. The electronic circuit claimed in claim 15 wherein the shared resource includes a scalable supply voltage for said set of processors.

20. The electronic circuit claimed in claim 15, further comprising a control circuit including a register coupled to said set of processors to indicate an asleep/awake state of each processor and said control circuit operable to isolate from the shared resource each processor indicated asleep by said register.

21. The electronic circuit claimed in claim 15 further comprising plural sensor circuits providing respective errors and wherein said arbitrating circuit is operable to generate a minimum of the respective errors.

22. The electronic circuit claimed in claim 15 wherein said arbitrating circuit is operable to generate a sleep output for controlling the shared resource when all the processors in said set of processors are asleep.

23. A telecommunication apparatus comprising:

a modem;

a set of processors that use a shared resource for operation of said set of processors, the shared resource having a plurality of resource levels, said modem coupled to at least one of said processors;

a set of shared resource control registers coupled to said set of processors, at least two of said shared resource control registers operable to store respective multi-bit values representing respectively requested levels among the plurality of resource levels, said processors each operable to supply a respective multi-bit value to at least one of the corresponding shared resource control registers;

an arbitrating circuit coupled to said shared resource control registers and responsive to output a multi-bit value representing an arbitrated resource level of the shared resource;

a scalable resource controller responsive to said arbitrating circuit to deliver the shared resource to the set of processors at substantially the arbitrated resource level of the shared resource represented by the multi-bit value output from said arbitrating circuit; and

a user interface coupled to said modem and to at least one of said processors.

24. A process of manufacturing an electronic circuit comprising fabricating a set of processors coupled to respective resource control registers responsive to multi-bit resource requests from said processors together with an arbitrating circuit responsive to said shared resource control registers to output a multi-bit value representing an arbitrated resource level.

25. The process of manufacturing claimed in claim 24 further including testing power management for the electronic circuit by supplying a controllable voltage for the set of processors, operating each processor to make respective voltage requests as the multi-bit resource requests, and arbitrating the voltage requests to automatically control the controllable voltage to establish the highest magnitude of the respective voltage requests.