METHOD, APPARATUS, AND SYSTEM FOR FLASH MEMORY

• US 20080162781A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Tran, Luan C., Haller, Gordon
• Granted Patent: US 7,808,053 B2
• Time in Patent Office: Days
• US Class Current: 711/101
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top surface of the plurality of layer, the first plurality of pitch-multiplied spacers being above the central region of the substrate, and a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary.

Claims

1. An apparatus comprising:

a substrate including a central region and a peripheral region;

a plurality of layers above a surface of the substrate, the plurality of layers covering at least a portion of the central region and at least a portion of the peripheral region adjacent to the portion of the central region covered by the plurality of layers;

a first plurality of pitch-multiplied spacers on a top surface of the plurality of layers, the first plurality of pitch-multiplied spacers being above the central region of the substrate and including at least one pitch-multiplied spacer having a surface at a boundary between the central region and the peripheral region; and

a second plurality of pitch-multiplied spacers on the top surface of the plurality of layers, the second plurality of pitch-multiplied spacers above the peripheral region and including at least one pitch-multiplied spacer having a surface at a distance from the at least one pitch multiplied spacer having a surface at the boundary, the distance no less than a width at the top surface between two of the plurality of pitch-multiplied spacers above the central region, and no more than a width at the top surface of a mask above an interconnect in the peripheral region and adjacent to the boundary.

2. The apparatus of claim 1, wherein the at least one pitch-multiplied spacer having an inner surface at a boundary between the central region and the peripheral region is above an area of the substrate forming an interconnect in the central region.

3. The apparatus of claim 1, wherein the first plurality of pitch-multiplied spacers and the second plurality of pitch-multiplied spacers includes silicon oxide.

4. The apparatus of claim 1, wherein each of the first plurality of pitch-multiplied spacers is above an area of the central region to be used as an interconnect line in an array of memory cells.

5. The apparatus of claim 4, wherein the array of memory cells includes NAND flash memory cells.

6. A method comprising:

providing a substrate having a central region and a peripheral region;

providing a plurality of layers on the substrate, the plurality of layers covering at least a portion of the central region and at least a portion of the peripheral regions adjacent to the portion of the central region covered by the plurality of layers;

the plurality of layers including a mask layer overlying the substrate, a first hard mask layer overlying the mask layer, a temporary layer overlying the first hard mask layer, a second hard mask layer overlaying the temporary layer, and a first photoresistive layer overlying the second hard mask layer;

forming a first photoresistive pattern in the first photoresistive layer;

transferring the first photoresistive pattern to the second hard mask layer and the temporary layer;

depositing a layer of spacer material over the pattern formed in the second hard mask layer and the temporary layer;

etching the layer of spacer material to remove spacer material from horizontal surfaces of the layer of spacer material to form a plurality of oxide spacers on a surface of the first hard mask layer wherein at least a first and a second oxide spacer are formed over the peripheral region, and at least a third oxide spacer is formed over the central region and having an inner surface at a boundary between the central region and the peripheral region;

forming a second photoresistive layer over the plurality of oxide spacers;

patterning the second photoresistive layer using a photolithographic process;

forming a mask by etching the patterned second photoresistive layer so that a layer of the photoresistive material fills and remains only in a space between the first and the second oxide spacer; and

transferring the pattern formed by the plurality of oxide spacers and the mask into the substrate to form at least one interconnect in the central region and at least one interconnect in the peripheral region separated by a trench in the substrate, the trench having a first side wall below the inner surface of the third oxide spacer and the trench having a second side wall below an inner surface of the first oxide spacer.

7. The method of claim 6, wherein forming the at least the first and the second oxide spacers over the peripheral region includes each of the first and the second oxide spacers having a width at the surface of the first hard mask layer substantially equal to a width of the third oxide spacer formed over the central region.

8. The method of claim 6, wherein filling the space between the first and the second oxide spacers with the photoresistive layer includes the space having an alignment margin of one half of a width of the first oxide spacer at the surface of the first hard mask layer.

9. The method of claim 6, transferring the pattern formed by the plurality of oxide spacers and the mask into the substrate to form at least one interconnect in the central region and at least one interconnect in the peripheral region includes an oxide etch.

10. The method of claim 6, further including processing the central region to include a plurality of memory cells.

11. The method of claim 10, wherein the plurality of memory cells includes NAND flash memory cells.

12. The method of claim 6, further including processing the peripheral region to include coupling one or more interconnect lines in the peripheral region to one or more interconnect lines in the central region.

13. The method of claim 6, wherein a width of the at least one interconnect in the peripheral region is about 200 nanometers.

14. The method of claim 6, wherein forming a first pattern in the first photoresistive layer includes patterning the first photoresistive layer using an inverted reticle.

15. The method of claim 6, wherein depositing a layer of spacer material over the pattern formed in the second hard mask layer and the temporary layer includes forming the layer of spacer material from silicon oxide.

16. The method of claim 6, wherein transferring the pattern formed by the plurality of oxide spacers and the mask into the substrate to form at least one interconnect in the central region and at least one interconnect in the peripheral region separated by a trench in the substrate includes the trench having a width less than a minimum size feature that may be formed by the photolithographic process.

17. A system comprising:

a processor;

a memory device coupled to the processor, the memory device including a central region having a plurality of memory cells coupled by a plurality of memory cell interconnects, the plurality of memory cell interconnects formed by pitch doubling, the memory device including a peripheral region having at least one peripheral interconnect coupled to one or more of the plurality of memory cell interconnects,

wherein at least a portion of the at least one peripheral interconnect is adjacent to one or more of the plurality of memory cell interconnects formed by pitch doubling, and wherein a width between the portion of the peripheral interconnect that is adjacent to the one or more memory cell interconnects is less than a one half of the pitch that can be formed using a photolithographic technique used to form the at least one peripheral interconnect.

18. The system of claim 17, wherein the peripheral interconnect is a select gate line coupled to at least one of the plurality of memory cells.

19. The system of claim 17, wherein the plurality of memory cells includes a plurality of NAND flash memory cell.

20. The system of claim 17, wherein the plurality of memory cells includes a programmable logic array including a plurality of NOR flash memory cells.

21. The system of claim 17, wherein the width is about 70 nanometers.

22. The system of claim 17, wherein a width of any one of the plurality of memory cell interconnects is no more than 60 nanometers.

23. The system of claim 17, wherein a width of the portion of the peripheral interconnect adjacent to one or more of the plurality of memory cell interconnects is about 200 nanometers.

24. The system of claim 17, wherein the processor and the memory device coupled to the processor are included in a laptop computer.