CACHING DEVICE FOR NAND FLASH TRANSLATION LAYER

• US 20080162792A1
• Filed: 08/20/2007
• Published: 07/03/2008
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Genesys Logic Incorporated
• Original Assignee: Genesys Logic Incorporated
• Inventors: Kuo, Tei-wei, Wu, Chin-hsien, Hsieh, Hsiang-chi
• Granted Patent: US 8,010,770 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Claims

1. A caching device for NAND flash translation layer positioned between a memory read/write controller and a flash memory, comprising:

an instruction register connecting the memory read/write controller from which the instruction for reading or writing the flash memory from the memory read/write controller is received and temporarily stored;

a logical address register connecting the memory read/write controller from which the logical address for reading or writing the flash memory from the memory read/write controller is received and temporarily stored;

a data register connecting the memory read/write controller so that the data for writing into or reading from the flash memory is temporarily stored;

an address translation unit which is a memory device containing address mapping table for the logical and physical addresses of the flash memory;

a microprocessor connecting the instruction register and the address translation unit responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation;

a caching control unit which is a programmable device containing the caching instruction and data for caching the logical and physical address mapping;

a pair of auxiliary controller where a first auxiliary controller interfaces the data and logical address registers with the microprocessor, and a second auxiliary controller interfaces the caching control unit with the microprocessor via which the caching instructions are fed into the microprocessor for execution;

a flash memory address register interfacing the address translation unit and the second auxiliary controller with the flash memory for temporarily storing the obtained physical address in accessing the flash memory via the second auxiliary controller; and

a caching instruction and data buffer area which is a memory device connecting the caching control unit for temporarily storing the caching instruction and data used by the caching control unit.

2. The caching device as claimed in claim 1, wherein the address translation unit is a random access memory.

3. The caching device as claimed in claim 1, wherein the caching control unit is a field-programmable gate array.

4. The caching device as claimed in claim 1, wherein the caching control unit is a read only memory.

5. The caching device as claimed in claim 1, wherein the caching instruction and data buffer area is a random access memory.