Obscuring memory access patterns

• US 20080162816A1
• Filed: 12/27/2006
• Published: 07/03/2008
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Sony Corporation Of America (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Wang, Hong, Jacobson, Quinn A., Buxton, Mark, Brickell, Ernie, Patel, Baiju
• Granted Patent: US 7,610,448 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions

Abstract

For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.

Claims

1. A method comprising

for each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache;

and

in response to the signal, reloading the set of memory locations into the cache.

2. The method of claim 1 further comprising loading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

3. The method of claim 1 wherein the signal further comprises an interrupt, the method further comprising registering a handler to respond to the signal.

4. The method of claim 1 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

5. The method of claim 2 wherein the signal comprises an interrupt, and wherein reloading the memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

6. The method of claim 3 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

7. The method of claim 3 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, the method further comprising logic of a processor detecting the eviction of data from the memory location from the cache and generating the interrupt.

8. The method of claim 1 further comprising the thread detecting that the thread has resumed execution following a context switch and the thread reloading the set of memory locations into the cache at least in part in response to the detecting.

9. A system comprising

a processor;

a memory communicatively coupled with the processor, further comprising a program thread (thread), where for each memory location in a set of memory locations associated with the thread, the thread is to set an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and

in response to the signal, to reload the memory locations into the cache.

10. The system of claim 9 wherein the thread is further to load the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

11. The system of claim 9 wherein the signal further comprises an interrupt, the thread further to register a handler to respond to the signal.

12. The system of claim 9 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

13. The system of claim 10 wherein the signal comprises an interrupt, and wherein reloading the set of memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

14. The system of claim 11 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

15. The system of claim 11 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, and wherein the system further comprises logic to detect the eviction of data from the memory location from the cache and to generate the interrupt.

16. The system of claim 9 wherein the thread is further to detect that the thread has resumed execution following a context switch and the to reload the set of memory locations into the cache at least in part in response to the detecting.

17. A tangible machine readable medium having stored thereon data that when accessed by a machine causes it to perform a method, the method comprising

for each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache;

and

in response to the signal, reloading the set of memory locations into the cache.

18. The machine readable medium of claim 17 wherein the method further comprises loading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

19. The machine readable medium of claim 17 wherein the signal further comprises an interrupt, the method further comprising registering a handler to respond to the signal.

20. The machine readable medium of claim 17 wherein the set of memory locations further comprises a set of memory locations having data, at least in part, private to the thread.

21. The machine readable medium of claim 18 wherein the signal comprises an interrupt, and wherein reloading the set of memory locations into the cache further comprises logic of a processor reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

22. The machine readable medium of claim 19 wherein reloading the set of memory locations into the cache further comprises the handler reloading the set of memory locations into the cache in at least one of

a random order;

and

a predetermined order.

23. The machine readable medium of claim 19 wherein setting the indication associated with the memory location further comprises setting an attribute bit associated with the cache line of the data from the memory location to a predetermined value, the method further comprising logic of a processor detecting the eviction of data from the memory location from the cache and generating the interrupt.

24. The machine readable medium of claim 19 wherein the method further comprises the thread detecting that the thread has resumed execution following a context switch and the thread reloading the set of memory locations into the cache at least in part in response to the detecting.