Non-Homogeneous Multi-Processor System With Shared Memory
First Claim
1. A system comprising:
- one or more first microprocessor with a first cache memory and a first address translation mechanism consistent with a set of page table entries; and
one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries.
0 Assignments
0 Petitions
Accused Products
Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
-
Citations
23 Claims
-
1. A system comprising:
-
one or more first microprocessor with a first cache memory and a first address translation mechanism consistent with a set of page table entries; and one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A system comprising:
-
one or more first microprocessors with a first cache memory and a first address translation mechanism consistent with a set of page table entries, wherein each of the first processors include a reduced instruction set computer architecture with memory access governed by page and segment tables, and the set of page table entries is consistent with the reduced instruction set computer architecture; one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries, wherein the second processors are single instruction multiple data processors with a unified register file and sequential instruction set semantics; and a bus interconnecting the first processors and the second processors, the bus supporting coherent direct memory access.
-
-
23. A system comprising:
-
one or more first microprocessor with a first cache memory and a first address translation mechanism consistent with a set of page table entries, wherein an operating system executes on one of the first processors; and one or more second processors with an attached direct memory access controller with a second address translation mechanism consistent with the set of page table entries, wherein the second processors access a system memory by issuing direct memory access commands that specify virtual memory addresses, the direct memory access controller adapted to translate between the virtual memory addresses and real memory addresses.
-
Specification