System and apparatus for group data operations

• US 20080162882A1
• Filed: 07/27/2007
• Published: 07/03/2008
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Incorporated
• Inventors: Moussouris, John, Hansen, Craig, Massalin, Alexia
• Granted Patent: US 7,660,973 B2
• Time in Patent Office: Days
• US Class Current: 712/210
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Claims

1. A programmable processor comprising:

(a) an instruction path and a data path;

(b) an external interface operable to receive data from an external source and communicate the received data over the data path;

(c) a register file comprising a plurality of registers coupled to the data path; and

(d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions that each operates on variable-size segments of data in an operand register, each segment consisting of a plurality of data elements, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file.

2. The programmable processor of claim 1 wherein the plurality of swap instructions comprises first, second, third, fourth, fifth, and sixth swap instructions,

wherein for the first swap instruction, the data elements are each 8 bits wide, and the segments are each 16 bits wide,

wherein for the second swap instruction, the data elements are each 8 bits wide, and the segments are each 32 bits wide,

wherein for the third swap instruction, the data elements are each 16 bits wide, and the segments are each 32 bits wide,

wherein for the fourth swap instruction, the data elements are each 8 bits wide, and the segments are each 64 bits wide,

wherein for the fifth swap instruction, the data elements are each 16 bits wide, and the segments are each 64 bits wide, and

wherein for the sixth swap instruction, the data elements are each 32 bits wide, and the segments are each 64 bits wide.

3. The programmable processor of claim 1 wherein the execution unit is further capable of executing a select instruction that operates on a plurality of data elements in a register in the register file and a plurality of indices in another register in the register file, each index selecting one of the plurality of data elements, to provide the data element selected by each index to a predetermined position in a catenated result returned to a register in the register file.

4. The programmable processor of claim 3 wherein the execution unit is further capable of executing a copy instruction that takes a scalar value within a register in the register file and duplicates the scalar value as every data element of a catenated result returned to a register in the register file.

5. The programmable processor of claim 4 wherein in response to decoding a single group shift left instruction specifying a shift amount as an immediate value, , the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are twice as wide as the first plurality of data elements.

6. The programmable processor of claim 5 wherein in response to decoding a single group shift left instruction specifying a register in the register file containing a shift amount, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

7. The programmable processor of claim 6 wherein in response to decoding a single group shift right instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

8. The programmable processor of claim 7 wherein in response to decoding a single group shift right instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are half as wide as the first plurality of data elements.

9. The programmable processor of claim 8 wherein in response to decoding a single group shift instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a first register in the register file, shift a subfield of the data element by the shift amount, to produce a plurality of shifted values, and

(b) insert each of the shifted values into a subfield within one of a second plurality of data elements in a second register in the register file.

10. The programmable processor of claim 9 wherein the execution unit is further capable of executing a shuffle instruction that interleaves a first plurality of data elements from a first register in the register file with a second plurality of data elements from a second register in the register file to produce a catenated result and provides the catenated result to a register in the register file.

11. The programmable processor of claim 10 wherein the execution unit is further capable of executing a shuffle instruction that de-interleaves a first plurality of data elements from a first register in the register file and a second plurality of data elements from a second register in the register file, by combining select elements from the first plurality of data elements with select elements from the second plurality of data elements to produce a catenated result, and provides the catenated result to a register in the register file.

12. A data processing system comprising:

a bus coupling components in the data processing system;

an external memory coupled to the bus; and

a programmable processor coupled to the bus, the processor comprising

(a) an instruction path and a data path,

(b) an external interface operable to receive data from an external source and communicate the received data over the data path,

(c) a register file comprising a plurality of registers coupled to the data path, and

(d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,

wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions that each operates on variable-size segments of data in an operand register, each segment consisting of a plurality of data elements, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file.

13. The system of claim 12 wherein the plurality of swap instructions comprises first, second, third, fourth, fifth, and sixth swap instructions,

wherein for the first swap instruction, the data elements are each 8 bits wide, and the segments are each 16 bits wide,

wherein for the second swap instruction, the data elements are each 8 bits wide, and the segments are each 32 bits wide,

wherein for the third swap instruction, the data elements are each 16 bits wide, and the segments are each 32 bits wide,

wherein for the fourth swap instruction, the data elements are each 8 bits wide, and the segments are each 64 bits wide,

wherein for the fifth swap instruction, the data elements are each 16 bits wide, and the segments are each 64 bits wide, and

wherein for the sixth swap instruction, the data elements are each 32 bits wide, and the segments are each 64 bits wide.

14. The system of claim 12 wherein the execution unit is further capable of executing a select instruction that operates on a plurality of data elements in a register in the register file and a plurality of indices in another register in the register file, each index selecting one of the plurality of data elements, to provide the data element selected by each index to a predetermined position in a catenated result returned to a register in the register file.

15. The system of claim 14 wherein the execution unit is further capable of executing a copy instruction that takes a scalar value within an operand register and duplicates the scalar value as every data element of a catenated result returned to a destination register.

16. The system of claim 15 wherein in response to decoding a single group shift left instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are twice as wide as the first plurality of data elements.

17. The system of claim 16 wherein in response to decoding a single group shift left instruction specifying a register in the register file containing a shift amount, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the most significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

18. The system of claim 17 wherein in response to decoding a single group shift right instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file.

19. The system of claim 18 wherein in response to decoding a single group shift right instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of data elements in a register in the register file, shift a subfield of the data element towards the least significant bit by the shift amount, to produce a second plurality of equal-sized data elements, and

(b) provide the second plurality of data elements as a catenated result to a register in the register file, wherein the second plurality of data elements are half as wide as the first plurality of data elements.

20. The system of claim 19 wherein in response to decoding a single group shift instruction specifying a shift amount as an immediate value, the execution unit is operable to:

(a) for each of a first plurality of the data elements in a first register in the register file, shift a subfield of the data element by the shift amount, to produce a plurality of shifted values, and

(b) insert each of the shifted values into a subfield within one of a second plurality of data elements in a second register in the register file.

21. The system of claim 20 wherein the execution unit is further capable of executing a shuffle instruction that interleaves a first plurality of data elements from a first register in the register file with a second plurality of data elements from a second register in the register file to produce a catenated result and provides the catenated result to a register in the register file.

22. The system of claim 21 wherein the execution unit is further capable of executing a shuffle instruction that de-interleaves a first plurality of data elements from a first register in the register file and a second plurality of data elements from a second register in the register file, by combining select elements from the first plurality of data elements with select elements from the second plurality of data elements to produce a catenated result, and provides the catenated result to a register in the register file.