OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECUTRAL EVENTS TO PMU

• US 20080162972A1
• Filed: 12/29/2006
• Published: 07/03/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Or, P. Keong, Sistia, Krishnakanth, Liu, Yen-Cheng, Srinivasa, Ganapati
• Granted Patent: US 8,117,478 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Claims

1. A processor comprising:

a bus to detect whether an architectural event has occurred within a core; and

a power unit to cause a power sequence in response to occurrence of the architectural event.

2. The processor of claim 1 wherein the architecture events are EMON counters.

3. The processor of claim 1 wherein the power unit is a power control unit to manage thermal and power events for the core.

4. The processor of claim 1 wherein the bus is a serial push bus to connect all the architecture events in the core,

5. The processor of claim 4 wherein the bus includes various branches and wherein each branch monitors one core with all the one cores architecture events.

6. The processor of claim 5 wherein the bus to send all data collected from the architecture events to the power unit.

7. The processor of claim 1 further comprising a shared last level cache.

8. The processor of claim 1 further comprising functional unit coupled to the power unit.

9. The processor of claim 1 wherein the bus, power unit, a plurality of cores or a last level cache are on the same integrated circuit die.

10. A method comprising:

generating a signal to indicate an occurrence of an architectural event;

causing an power sequence based on the occurrence of the architecture event.

11. The method of claim 10 wherein causing a power sequence comprises powering up the core if reserve power is available.

12. The method of claim 10 wherein causing a power sequence comprises remaining idle if no reserve power is available.

13. The method of claim 10 wherein causing a power sequence comprises powering down the core.

14. The method of claim 10 wherein the generating the signal occurs for every core.

15. A system comprising:

a memory to store architecture event data corresponding to one or more events that are to be monitored;

a bus to detect whether an architectural event has occurred within a core; and

a power unit to cause a power sequence in response to occurrence of the architectural event.

16. The system of claim 15 wherein the architecture events are EMON counters.

17. The system of claim 15 wherein the power unit is a power control unit to manage thermal and power events for the core.

18. The system of claim 15 wherein the bus is a serial push bus to connect all the architecture events in the core.

19. The system of claim 18 wherein the bus includes various branches and wherein each branch monitors one core with all the one cores architecture events.

20. The system of claim 19 wherein the bus to send all data collected from the architecture events to the power unit.

21. The system of claim 15 further comprising a shared last level cache.

22. The system of claim 15 further comprising functional unit coupled to the power unit.

23. The system of claim 15 wherein the bus, power unit, a plurality of cores or a last level cache are on the same integrated circuit die.

24. The system of claim 15 further comprising an audio device coupled to the memory.