METHOD OF FACILITATING RELIABLY ACCESSING FLASH MEMORY

• US 20080163031A1
• Filed: 12/27/2007
• Published: 07/03/2008
• Est. Priority Date: 12/28/2006
• Status: Active Grant

• Current Assignee: Genesys Logic Incorporated
• Original Assignee: Genesys Logic Incorporated
• Inventors: Kuo, Tei-wei, Hsieh, Jen-wei, Hsieh, Hsiang-chi
• Granted Patent: US 8,010,876 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Claims

1. A method of facilitating reliably accessing flash memory comprising the steps of:

(a) determining whether data is to be read out or write in;

(b) if the result of step(a) is to be write-in, coding a number of N write-in data to generate a number of K extra data, generating the first error correction code by using an error-correcting operation to the N write-in data and K extra data, and storing the N write-in data and the generated K extra data into the data area and the first ECC into the spare area; and

(c) if the result of step(a) is to be read out, allocating a plurality of counters in the main memory;

(d) each bit in the data area of the target flash-memory page'"'"'s data area corresponding to a counter for accumulating a number of differences between the first and the second error correction codes (ECCs) associated to each flash-memory page;

(e) reading data from the data area of the flash-memory page to generate the second ECC and reading the first ECC from the spare area of the flash-memory page, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting a number of M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data by using reverse operation of original adopted operation of coding in step (b).

2. The method of claim 1, wherein a capacity of each data area of a flash-memory page is 512×

8 bits.

3. The method of claim 1, wherein the plurality of counters are composed of a counter array in characteristic of sequential addresses.

4. The method of claim 1, wherein the coding of step (b) is analogous with an operation exclusive OR operation.

5. The method of claim 1, wherein the step (b) comprises the steps of:

(e1) coding the N write-in data by using random-coding operation to generate the K extra data;

(e2) performing error-correcting with the N write-in data and the K extra data to generate the first error correction code; and

(e3) storing the N write-in data and the K extra data into a data area 111 of an assigned flash-memory page, and storing the first ECC into the spare area 112 of the assigned flash-memory page.

6. The method of claim 1, wherein the step (e) comprises the steps of:

(f1) reading the N write-in data and the K extra data stored in the data area and corresponding first error correction code in the spare area;

(f2) selecting a number of M data from the N write-in data and K extra data as factors for data retrieving;

(f3) retrieving the N write-in data D₁˜

D_n by decoding the selected M data;

(f4) determining whether the decoded data is correct? If it is, go to step (f6), if not go to step (f5);

(f5) determining whether the repeated times over a threshold regarding to an upper limitation of misreading? If it is, go to step (f51), if not, go to step (f52);

(f51) alarming a failure of reading operation of the flash-memory page; and

(f52) selecting another set of M data from the N write-in data D₁˜

D_n and K extra data T₁˜

T_k stored in the data area; and

(f6) returning the correct data.

7. The method of claim 6, wherein the step (f2) comprising the steps of:

(f21) clearing the counter corresponding to each bit in the data area;

(f22) reading the N write-in data and the K extra data stored in the data area of the assigned flash-memory page;

(f23) reading the first ECC stored in the spare area of the assigned flash-memory page;

(f24) calculating the second ECC based on the N write-in data and the K extra data;

(f25) comparing the first ECC and the second ECC bit by bit;

(f26) determining whether the compared bit of the first ECC and the second ECC is identical, if it is, go to step (f261), if not, go to step (f262);

(f261) Since each bit in the ECC dominates a set of bits in the data area, add the value of those counters dominated by the bit by one.;

(f262) determining whether the compared bit is the last bit, if it is, go to step (f27), if not, go to step (f263);

(f263) keeping on a comparison of the next bit; and

(f27) determining whether to select the bit in the data area based on the count of the corresponding counter.