METHODS, DESIGNS, DEFECT REVIEW TOOLS, AND SYSTEMS FOR DETERMINING LOCATIONS ON A WAFER TO BE REVIEWED DURING DEFECT REVIEW

• US 20080163140A1
• Filed: 12/05/2007
• Published: 07/03/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Chang, Ellis, Saidin, Zain K., Fouquet, Christophe, Abbott, Gordon
• Granted Patent: US 7,904,845 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects

Abstract

Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

Claims

1. A computer-implemented method for determining locations on a wafer to be reviewed during defect review, comprising:

acquiring coordinates of defects detected by two or more inspection systems, wherein the defects do not comprise defects detected on the wafer; and

determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

2. The method of claim 1, wherein the defects comprise defects in a design, defects detected on a reticle, defects on the reticle detected by process window characterization, or some combination thereof, and wherein the two or more inspection systems comprise a design inspection system, a reticle inspection system, a process window characterization system, or some combination thereof.

3. The method of claim 1, wherein said determining comprises determining the coordinates of the locations on the wafer to be reviewed as a single set of coordinates.

4. The method of claim 1, further comprising creating a recipe for the defect review using the coordinates of the locations and a design for the wafer, wherein said creating is performed offline without imaging the wafer or defects on the wafer.

5. The method of claim 1, further comprising determining if systematic defects detected on the wafer by inspection of the wafer are correlated to the defects detected by the two or more inspection systems.

6. The method of claim 1, further comprising creating an encrypted and secured file comprising the coordinates of the locations on the wafer to be reviewed during the defect review.

7. The method of claim 1, further comprising identifying the locations on the wafer during the defect review by comparing images acquired during the defect review at the coordinates of the locations to a design for the wafer.

8. The method of claim 1, further comprising selecting a method for automatic defect location to be performed during the defect review from all available methods for the automatic defect location based on a design for the wafer.

9. The method of claim 1, further comprising identifying the locations on the wafer during the defect review by comparing images acquired during the defect review at the coordinates of the locations to a design for the wafer and simulated images that illustrate how the design would be printed on the wafer at different values of one or more parameters of a process performed on the wafer.

10. The method of claim 9, further comprising determining information about the process based on results of said comparing.

11. The method of claim 1, further comprising determining, during the defect review, if additional locations on the wafer are to be reviewed based on results of the defect review at the locations and a design for the wafer proximate the locations.

12. The method of claim 1, further comprising determining, during the defect review, if an additional operation is to be performed at the locations on the wafer based on results of the defect review at the locations and a design for the wafer.

13. The method of claim 1, further comprising acquiring results of inspection of the wafer and randomly selecting defects detected by the inspection of the wafer from the results of the inspection for review during the defect review, wherein the locations on the wafer constitute a systematic defect sample, wherein the randomly selected defects constitute a random sample, and wherein the defect review for the systematic defect sample and the random sample is performed in the same defect review process.

14. The method of claim 13, wherein prior to the defect review, if analysis of the results of the inspection indicates that one or more of the defects detected by the inspection of the wafer are systematic defects, the method further comprises adding the one or more of the defects to the systematic defect sample and if the one or more of the defects are included in the random sample, removing the one or more of the defects from the random sample.

15. The method of claim 13, further comprising generating a Pareto chart illustrating results of the defect review of the systematic defect sample and the random sample.

16. The method of claim 13, further comprising classifying defects in the random sample identified by the defect review as systematic defects using design-based binning.

17. The method of claim 1, further comprising using results of the defect review to determine locations of the systematic defects on the wafer and using a design for the wafer to determine additional locations on the wafer at which the systematic defects can be found.

18. The method of claim 1, further comprising using results of the defect review to determine a kill ratio for defects found during the defect review by comparing the found defects to a design for the wafer and to determine a yield impact for the defects found during the defect review by comparing dimensions of the defects found during the defect review to dimensions of the design.

19. The method of claim 1, further comprising altering one or more parameters of at least one of the two or more inspection systems based on results of the defect review.

20. The method of claim 1, further comprising storing information about the defects detected by the two or more inspection systems and results of the defect review in a database for systematic defects.

21. The method of claim 1, further comprising using information about the defects detected by the two or more inspection systems and results of the defect review to generate a design for a test object, wherein the design comprises all designs that can be used for monitoring a process performed on the wafer.

22. The method of claim 1, further comprising using information about the defects detected by the two or more inspection systems and results of the defect review to generate a design for a test structure configured to be monitored for systematic defects and to add the design to a design to be printed on product wafers.

23. The method of claim 1, further comprising using information about the defects detected by the two or more inspection systems and results of the defect review to generate a design for a monitor wafer configured to be monitored for systematic defects after processing of the monitor wafer with product wafers, wherein the design comprises critical designs for the product wafers and variations of the critical designs corresponding to process windows for the critical designs.

24. A carrier medium, comprising program instructions executable on a computer system for performing a computer-implemented method for determining locations on a wafer to be reviewed during defect review, wherein the computer-implemented method comprises:

acquiring coordinates of defects detected by two or more inspection systems, wherein the defects do not comprise defects detected on the wafer; and

determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.

25. A system configured to determine locations on a wafer to be reviewed during defect review, comprising:

two or more inspection systems configured to detect defects, wherein the defects do not comprise defects detected on the wafer; and

a computer system coupled to the two or more inspection systems such that the computer system can acquire coordinates of the defects detected by the two or more inspection systems, wherein the computer system is configured to determine coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.