Thin film transistor substrate and method of producing the same

• US 20080164471A1
• Filed: 11/13/2007
• Published: 07/10/2008
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Byeong-Jin, Hong, Sun-young, Shin, Won-suk, Choung, Jong-hyun, Park, Hong-sick, Kim, Bong-kyun
• Granted Patent: US 7,824,972 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor substrate that has reduced production cost and defect rate is presented. The thin film transistor substrate includes a gate wiring line formed on an insulating substrate and including a gate electrode, a data wiring line formed on the gate wiring line and including a source electrode and a drain electrode, a passivation layer pattern formed on parts of the data wiring line other than the drain electrode and a pixel region, and a pixel electrode electrically connected to the drain electrode. The pixel electrode includes zinc oxide.

Claims

1. A thin film transistor substrate comprising:

a gate wiring line formed on an insulating substrate and comprising a gate electrode;

a data wiring line formed on the gate wiring line and comprising a source electrode and a drain electrode;

a passivation layer pattern formed on the data wiring line except on a part of the drain electrode and a pixel region; and

a pixel electrode electrically connected to the drain electrode and comprising zinc oxide.

2. The thin film transistor substrate of claim 1, wherein the pixel electrode comprises one or more of Al₂O₃, AlF₃, B₂O₃, Ga₂O₃, Y₂O₃, SiO₂, SiO, TiO₂, ZrO₃, HfO₂, and GeO₂ as an additive.

3. The thin film transistor substrate of claim 1, wherein the pixel electrode comprises aluminum-doped zinc oxide (ZAO).

4. The thin film transistor substrate of claim 1, further comprising:

a gate insulating layer pattern formed on the gate wiring line except on the pixel region.

5. The thin film transistor substrate of claim 4, wherein the pixel electrode contacts the insulating substrate in the pixel region.

6. The thin film transistor substrate of claim 1, further comprising:

an active layer pattern provided between the gate wiring line and the data wiring line,

wherein the active layer pattern covers the entire data wiring line.

7. The thin film transistor substrate of claim 1, further comprising:

an active layer pattern provided between the gate wiring line and the data wiring line,

wherein the active layer pattern is an island formed on the gate electrode.

8. A thin film transistor substrate comprising:

a gate wiring line formed on an insulating substrate and comprising a gate electrode;

a data wiring line formed on the gate wiring line and comprising a source electrode and a drain electrode;

a passivation layer pattern formed on the data wiring line except on a part of the drain electrode and a pixel region; and

a pixel electrode electrically connected to the drain electrode, contacting the insulating substrate and comprising zinc oxide.

9. A method of producing a thin film transistor substrate, the method comprising:

forming a gate wiring line comprising a gate electrode on an insulating substrate;

forming a data wiring line comprising a source electrode and a drain electrode on the gate wiring line;

forming a passivation layer pattern on the data wiring line except for a part of the drain electrode and a pixel region; and

forming a pixel electrode electrically connected to the drain electrode and comprising zinc oxide.

10. The method of claim 9, wherein the forming of the passivation layer pattern comprises:

forming a passivation layer on the gate wiring line and the data wiring line;

forming a photoresist pattern on the passivation layer to remove the passivation layer from the drain electrode and the pixel region; and

overetching the passivation layer using the photoresist pattern as an etching mask.

11. The method of claim 10, wherein:

the photoresist pattern comprises a first region and a second region;

the first region is formed on the gate wiring line and the data wiring line with the exception of a part of the drain electrode; and

the second region is formed between an end of the drain electrode and the pixel region, the second region being thinner than the first region.

12. The method of claim 11, wherein the overetching of the passivation layer comprises:

performing a first etching of the passivation layer using the photoresist pattern as the etching mask;

stripping the second region; and

performing a second etching of the passivation layer so that an undercut is formed in the passivation layer under the first region.

13. The method of claim 10, wherein the photoresist pattern is formed on the gate wiring line and the data wiring line with the exception of a part of the drain electrode.

14. The method of claim 12, wherein the overetching of the passivation layer comprises:

etching the passivation layer using the photoresist pattern as the etching mask so that the undercut is formed in the passivation layer.

15. The method of claim 10, wherein the forming of the pixel electrode comprises:

applying a conductive substance for the pixel electrode to the entire surface of the insulating substrate including where the photoresist pattern is formed; and

performing a lift off process of the conductive substance for the pixel electrode formed on the photoresist pattern by removing the photoresist pattern to form the pixel electrode.

16. The method of claim 15, wherein the performing of the lift off process of the conductive substance for the pixel electrode comprises:

removing the photoresist pattern from the gate wiring line and the data wiring line with the exception of a part of the drain electrode using a stripper so as to remove the conductive substance for the pixel electrode from the gate wiring line and the data wiring line with the exception of a part of the drain electrode.

17. The method of claim 16, wherein the conductive substance for the pixel electrode remains in the stripper after the performing of the lift off process, and the stripper is reused after being filtered and recycled through a stripper tank after the performing of the lift off process, and the conductive substance for the pixel electrode remaining in the stripper is dissolved in the stripper during recycling.

18. The method of claim 15, wherein the conductive substance for the pixel electrode comprises one or more of Al₂O₃, AlF₃, B₂O₃, Ga₂O₃, Y₂O₃, SiO₂, SiO, TiO₂, ZrO₃, HfO₂, and GeO₂ as an additive.

19. The method of claim 15, wherein the conductive substance for the pixel electrode comprises aluminum-doped zinc oxide (ZAO).

20. The method of claim 9, further comprising:

forming a gate insulating layer on the gate wiring line after the forming of the gate wiring line,

wherein the forming of the passivation layer pattern comprises etching the gate insulating layer to form a gate insulating layer pattern.

21. The method of claim 20, wherein the pixel electrode contacts the insulating substrate in the pixel region.

22. The method of claim 9, further comprising:

forming an active layer on the gate wiring line before the forming of the data wiring line,

wherein the forming of the passivation layer pattern comprises etching the active layer to form an active layer pattern.

23. The method of claim 9, wherein the active layer pattern and the data wiring line are formed using the same mask.