Power Device with Trenches Having Wider Upper Portion than Lower Portion

• US 20080164519A1
• Filed: 03/17/2008
• Published: 07/10/2008
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Becky Losee, Dean Probst, Robert Herrick
• Inventors: Probst, Dean, Herrick, Robert, Losee, Becky
• Granted Patent: US 7,595,524 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In accordance with an embodiment of the present invention, a FET is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Claims

1. A semiconductor device comprising:

a trench in a silicon layer; and

a source region formed in the silicon layer adjacent each sidewall of the trench, wherein the trench sidewalls are shaped along the silicon layer such that the trench sidewalls fan out near the top of the trench to extend directly over a substantial portion of each source region.

2. The semiconductor device of claim 1 further comprising:

a gate electrode partially filling the trench but overlapping each source region along the trench sidewalls; and

an insulating layer substantially filling a remaining portion of the trench over the gate electrode, wherein a sidewall of the insulating layer in the trench together with a sidewall of a corresponding source region form a sidewall of a contact opening through which contact is made at least with the source region.

3. The semiconductor device of claim 2 further comprising:

a body region adjacent each trench sidewall, the body regions being of opposite conductivity type to that of the source regions; and

a metal layer contacting the body regions and the source regions through the contact opening.

4. The semiconductor device of claim 1 wherein the insulating layer is fully contained within the trench.

5. A trench MOSFET comprising:

a plurality of trenches formed in silicon layer such that sidewalls of each trench along the silicon layer fan out near the top of the trench to extend directly over a portion of the silicon layer;

a gate electrode partially filling each trench;

an insulating layer substantially filling a remaining portion of each trench, the insulating layer in each trench being fully contained within the trench;

a plurality of body regions in the silicon layer, each body region extending between two adjacent trenches; and

a source region formed adjacent each trench sidewall in the body regions such that the insulating layer extends directly over at least a portion of each source region, the source regions being of opposite conductivity type to the body regions.

6. The trench MOSFET of claim 5 wherein sidewalls of the insulating layer in each trench together with corresponding sidewalls of the source regions form a contact opening between every two adjacent trenches.

7. The trench MOSFET of claim 6 further comprising:

a metal layer contacting the body region and the source regions through the contact openings.

8. The trench MOSFET of claim 5 wherein the gate electrode in each trench overlaps corresponding source regions but is recessed below the portion of the trench sidewalls where the trench sidewalls start to fan out.

9. The trench MOSFET of claim 5 wherein:

the silicon layer further comprises an epitaxial layer extending over a substrate, the body regions being formed in the epitaxial layer, and

the substrate, the epitaxial layer, and the source regions have a conductivity type opposite that of the body regions.

10. A semiconductor device comprising:

a plurality of trenches in a silicon layer;

an insulating layer filling an upper portion of each trench, the insulating layer being contained within each trench; and

a source region formed in the silicon layer adjacent each trench sidewall such that a sidewall of the insulating layer in each trench together with a sidewall of a corresponding source region form a contact opening between every two adjacent trenches.

11. The semiconductor device of claim 10 wherein the insulating layer in each trench extends over a substantial portion of corresponding source regions, the semiconductor device further comprising:

a metal layer contacting at least the source regions through the contact openings.