CMOS IMAGE SENSOR

• US 20080164552A1
• Filed: 12/26/2007
• Published: 07/10/2008
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Hwang, Sang-Il
• Granted Patent: US 7,713,775 B2
• Time in Patent Office: Days
• US Class Current: 257/432
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

Embodiments relate to a CMOS image sensor and to a method for manufacturing a CMOS image sensor that may disperse stray beam between microlenses. According to embodiments, the method for manufacturing the CMOS image may include forming an interlayer dielectric layer on a semiconductor substrate including a plurality of photo diodes, forming a color filter layer corresponding to the photo diodes on the interlayer dielectric layer, forming a planarization layer on the color filter layer, forming microlenses on the planarization layer after depositing an insulating layer over the microlenses, forming a trench in a concave lens shape in the insulating layer between the microlenses, and forming a concave lens gap-filling insulating materials inside the trench. In embodiments, concave lenses may be formed between microlenses in a CMOS image sensor and stray beams between the microlenses may be dispersed and recondensed into the microlenses.

Claims

1. A method, comprising:

forming an interlayer dielectric layer over a semiconductor substrate including a plurality of photo diodes;

forming a color filter layer corresponding to locations of the photo diodes over the interlayer dielectric layer;

forming a planarization layer over the color filter layer;

forming microlenses over the planarization layer;

depositing an insulating layer over the microlenses;

forming a trench having a concave lens shape in the insulating layer between the microlenses; and

forming a concave lens gap-filling insulating material inside the trench.

2. The method of claim 1, wherein forming the microlenses comprises:

forming a microlens pattern by applying and patterning a microlens resist layer over the planarization layer; and

forming each of the microlenses in a round shape by reflowing the microlens pattern.

3. The method of claim 2, wherein the microlens resist layer comprises material having larger refractive index than that of the insulating layer.

4. The method of claim 2, wherein the microlens pattern is reflowed using an annealing process.

5. The method of claim 1, wherein the insulating layer comprises SiO₂.

6. The method of claim 1, wherein the trench is formed over the insulating layer using a micro trench phenomenon.

7. The method of claim 1, wherein the trench is formed by performing a rectractive ion etching (RIE) on the insulating layer to form a micro trench profile having a concave lens shape.

8. The method of claim 1, wherein the gap-filling insulating material inside the trench comprises a low temperature oxide (LTO) comprising SiO₂.

9. The method of claim 1, wherein the trench is formed in a process condition with a Pressure of 5˜

300 mTorr, a Source Power of 50˜

2000 W, a Bias Power of 50˜

2000 W, and O2 gas of 1˜

50 sccm.

10. The method of claim 1, wherein the trench is formed in a process condition with CF4 gas of 1˜

200 sccm, CH2F2 gas of 1˜

10 sccm, Ar gas of 10˜

900 sccm, N2 gas of 10˜

200 sccm.

11. A device, comprising

an interlayer dielectric layer over a semiconductor substrate including a plurality of photo diodes;

a color filter layer corresponding to locations of the photo diodes over the interlayer dielectric layer;

microlenses over the color filter layer;

an insulating layer over the microlenses;

a trench having a concave lens shape in the insulating layer between the microlenses; and

a concave lens gap-filling insulating material inside the trench.

12. The device of claim 11, further comprising a planarization layer over the color filter layer, wherein the microlenses are formed over the planarization layer.

13. The device of claim 12, wherein the microlenses are formed by forming a microlens pattern by applying and patterning a microlens resist layer over the planarization layer, and forming each of the microlenses in a round shape by reflowing the microlens pattern.

14. The device of claim 13, wherein the microlens resist layer comprises material having larger refractive index than that of the insulating layer.

15. The device of claim 14, wherein the microlens pattern is reflowed using an annealing process.

16. The device of claim 15, wherein the insulating layer comprises SiO₂.

17. The device of claim 15, wherein the gap-filling insulating material inside the trench comprises a low temperature oxide (LTO) comprising SiO₂.

18. The device of claim 12, wherein the trench is formed in a process condition with a Pressure of 5˜

300 mTorr, a Source Power of 50˜

2000 W, a Bias Power of 50˜

2000 W, and O2 gas of 1˜

50 sccm.

19. The device of claim 12, wherein the trench is formed in a process condition with CF4 gas of 1˜

200 sccm, CH2F2 gas of 1˜

10 sccm, Ar gas of 10˜

900 sccm, N2 gas of 10˜

200 sccm.