Zirconium and Hafnium Boride Alloy Templates on Silicon for Nitride Integration Applications

• US 20080164570A1
• Filed: 01/04/2008
• Published: 07/10/2008
• Est. Priority Date: 01/04/2007
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Kouvetakis, John, Roucka, Radek
• Granted Patent: US 8,803,194 B2
• Time in Patent Office: Days
• US Class Current: 257/607
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 33/007 comprising nitride compounds

Abstract

Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.

Claims

1. A semiconductor structure comprising a substrate and an epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B and one or more element selected from the group consisting of Zr, Hf and Al;

and the epitaxial layer has a thickness greater than 50 nm.

2. The semiconductor structure of claim 1, wherein the epitaxial layer has one or more properties selected from the group consisting of,

(i) relaxed at 900°

C.;

(ii) thermally decoupled from the substrate; and

(iii) an atomically flat surface.

3. The semiconductor structure of claim 1 wherein the epitaxial layer comprises ZrB₂, AlB₂, or HfB₂.

4. The semiconductor structure of claim 1 wherein the epitaxial layer comprises an alloy selected from the group consisting of Hf_xZr₁₋

xB₂, Hf_xAl<sub>1−

x</sub>B₂, Zr_xAl<sub>1−

x</sub>B₂, and Zr_zHf_yAl<sub>1−

z−

y</sub>B₂, wherein the sum of z and y is less than or equal to 1.

5. The semiconductor structure of claim 1, further comprising an active layer formed over the epitaxial layer.

6. The semiconductor structure of claim 5, wherein the active layer has one or more properties selected from the group consisting of

(i) lattice-matched to the epitaxial film;

(ii) comprising a Group III nitride; and

(iii) comprising a compound which is selected from the group consisting of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, and SiCAlN, or mixtures thereof.

7. The semiconductor structure of claim 1, wherein the substrate comprises Si, Al₂O₃, SiC or GaAs.

8. The semiconductor structure of claim 7 wherein the substrate comprises Si(100) or Si(111).

9. The semiconductor structure of claim 7 wherein the substrate comprises a miscut Si(111) substrate.

10. The semiconductor structure of claim 1, wherein the epitaxial layer is formed by molecular beam epitaxy or chemical vapor deposition.

11. The semiconductor structure of claim 1, wherein the epitaxial layer is formed directly on the substrate, and comprises B and two or more elements selected from the group consisting of Zr, Hf and Al.

12. The semiconductor structure of claim 11, further comprising an epitaxial HfB₂ layer formed directly on the epitaxial layer.

13. The semiconductor structure of claim 1, wherein the epitaxial layer is formed directly on the substrate and comprises ZrB₂.

14. The semiconductor structure of claim 13, further comprising an epitaxial HfB₂ layer formed directly on the epitaxial layer.

15. A method for forming an epitaxial buffer layer over a substrate comprising,

contacting a substrate with a precursor gas at a temperature and a pressure suitable for depositing an epitaxial buffer layer over the substrate, the epitaxial buffer layer having a thickness of greater than about 50 nm, wherein

the precursor gas comprises hydrogen and about 0.1-5 v/v % of a precursor source, wherein the precursor source comprises Zr(BH₄)₄, Hf(BH₄)₄, an Al source, or mixtures thereof.

16. The method of claim 15, wherein the substrate comprises Si, Al₂O₃, SiC or GaAs.

17. The method of claim 16 wherein the substrate comprises Si(100) or Si(111).

18. The method of claim 15 wherein the substrate comprises a miscut Si(111) substrate.

19. The method of claim 15 wherein the epitaxial buffer layer comprises ZrB₂, AlB₂, or HfB₂.

20. The method of claim 15 wherein the epitaxial buffer layer comprises an alloy selected from the group consisting of Hf_xZr₁₋

xB₂, Hf_xAl<sub>1−

x</sub>B₂, Zr_xAl<sub>1−

x</sub>B₂, and Zr_zHf_yAl<sub>1−

z−

y</sub>B₂, wherein the sum of z and y is less than or equal to 1.

21. The method of claim 15 wherein the temperature ranges from about 850°

C. to about 950°

C.

22. The method of claim 15 wherein the pressure ranges from about 1×

10<sup>−

4</sup> Torr to 1×

10<sup>−

9</sup> Torr.

23. The method of claim 15, wherein the epitaxial layer is formed by molecular beam epitaxy or chemical vapor deposition.

24. A method for integrating Group III nitrides onto a substrate comprising,

forming a buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, having a thickness greater than about 50 nm over a substrate;

and

forming a Group III nitride layer over the buffer layer.

25. The method of claim 24, wherein the buffer layer has one or more properties selected from the group consisting of,

(i) thermally decoupled from the substrate;

(ii) a mismatch strain which is essentially thermally constant over a temperature range of room temperature to 900°

C.;

(iii) relaxed at 900°

C.; and

(iv) an atomically flat surface.

26. The method of claim 24, wherein the buffer layer comprises ZrB₂, AlB₂, or HfB₂.

27. The method of claim 24 wherein the buffer layer comprises Hf_xZr₁₋

xB₂, Hf_xAl<sub>1−

x</sub>B₂, Zr_xAl<sub>1−

x</sub>B₂, or Zr_zHf_yAl<sub>1−

z−

y</sub>B₂, wherein the sum of z and y is less than or equal to 1.

28. The method of claim 24, wherein the Group III nitride layer has one or more properties selected from the group consisting of,

(i) lattice-matched to the buffer layer;

and

(ii) comprising a compound selected from the group consisting of GaN, AlGaN, InGaN, AlInGaN, AlN, InN, SiCAlN, and mixtures thereof.

29. The method of claim 24, wherein the substrate comprises Si, Al₂O₃, SiC or GaAs.

30. The method of claim 24 wherein the substrate comprises Si(111) or Si(100).

31. The method of claim 24 wherein the substrate comprises a miscut Si(111) substrate.

32. The method of claim 24, wherein the buffer layer is formed by molecular beam epitaxy or chemical vapor deposition.

33. A method for tuning the reflectivity of a buffer layer comprising,

forming a buffer layer of an alloy of the formula Hf_xZr₁₋

xB₂ having a thickness greater than about 50 nm and a reflectivity over a substrate, wherein x is a predetermined value from 0 to 1, and wherein the reflectivity of the buffer layer is greater than a layer of ZrB₂ having an identical thickness as the buffer layer.

34. A method for tuning the lattice constant of a buffer layer comprising, forming a buffer layer of an alloy of the formula Hf_xZr₁₋

xB₂ having a thickness greater than about 50 nm, and forming an active layer over the buffer layer, wherein x is a predetermined value from 0 to 1, and wherein the active layer is lattice matched to the buffer layer,