Semiconductor apparatus using ion beam

• US 20080164819A1
• Filed: 01/08/2008
• Published: 07/10/2008
• Est. Priority Date: 01/08/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jin-Seok, Shin, Chul-Ho, Hwang, Sung-Wook, Lee, Yung Hee Yvette
• Application Number:
  US12/007,187
• Publication Number:
  US 20080164819A1
• Time in Patent Office: Days
• US Class Current: 315/111.41
• CPC Class Codes: H01J 2237/0041 Neutralising arrangements
• CPC Class Codes: H01J 2237/061 Construction
• CPC Class Codes: H01J 27/024 Extraction optics, e.g. grids
• CPC Class Codes: H01J 37/08 Ion sources; Ion guns
• CPC Class Codes: H01J 37/305 for casting, melting, evaporating, or etching
• CPC Class Codes: H01J 37/3171 for ion implantation

Abstract

Provided is a semiconductor apparatus using an ion beam. The semiconductor apparatus may include a first grid to which a voltage applied. The voltage applied to the first grid may have the same potential level as that of a reference voltage applied to a wall portion of a plasma chamber in which plasma may be generated. The first grid may adjoin the plasma. Therefore, a potential level difference between the first grid and the wall portion of the plasma chamber may be zero, and thus the plasma may be stable.

Claims

1. A semiconductor apparatus comprising:

a plasma chamber including a wall portion to which a reference voltage is applied and an inner space in which plasma is generated; and

a plurality of grids adjacent to the plasma chamber inducing ion beams from the plasma, wherein

each of the grids includes a plurality of induction holes through which the ion beams pass,

a voltage having the same potential level as that of the reference voltage applied to a first grid, and

a voltage having a potential level different from that of the reference voltage applied to a last grid;

wherein

the first grid is the grid closest to the plasma, and the last grid is the grid farthest from the plasma.

2. The semiconductor apparatus of claim 1, wherein the ion beams are positive ion beams, and the voltage applied to the last grid has a potential level lower than that of the reference voltage.

3. The semiconductor apparatus of claim 2, wherein the plurality of grids includes at least one grid between the first and last grids, and

the at least one grid between the first and the last grids includes a flux adjustment grid, wherein

a voltage having a potential level lower than that of the reference voltage is applied to the flux adjustment grid.

4. The semiconductor apparatus of claim 3, wherein the voltage applied to the flux adjustment grid has a potential level lower than that of the voltage applied to the last grid.

5. The semiconductor apparatus of claim 1, wherein the ion beams are negative ion beams, and the voltage applied to the last grid has a potential level higher than that of the reference voltage.

6. The semiconductor apparatus of claim 5, wherein the plurality of grids includes at least one grid between the first and last grids, and

the at least one grid between the first and the last grids includes a flux adjustment grid, wherein

a voltage having a potential level higher than that of the reference voltage is applied to the flux adjustment grid.

7. The semiconductor apparatus of claim 6, wherein the voltage applied to the flux adjustment grid has a potential level higher than that of the voltage applied to the last grid.

8. The semiconductor apparatus of claim 1, further comprising:

a neutralizing unit for converting the ion beams into neutral beams, wherein the plurality of grids is between the plasma chamber and the neutralizing unit.

9. The semiconductor apparatus of claim 8, wherein a voltage having the same potential level as that of the voltage applied to the last grid is applied to the neutralizing unit.

10. The semiconductor apparatus of claim 8, wherein the neutralizing unit includes a plurality of reflection plates, wherein the plurality of reflection plates having an angle to the ion beams.

11. The semiconductor apparatus of claim 8, wherein the neutralizing unit includes a plate through which a plurality of penetration holes is formed, and the ion beams are converted into neutral beams while passing through the penetration holes.

12. The semiconductor apparatus of claim 11, wherein the plurality of penetration holes of the neutralizing unit is aligned with the induction holes of the plurality of grids, and the penetration holes have an aspect ratio greater than that of the induction holes.

13. The semiconductor apparatus of claim 1, wherein the wall portion of the plasma chamber comprises:

an outer wall formed of a conductive material; and

an inner wall on the outer wall and formed of a dielectric material, wherein

the inner wall adjoins the inner space of the plasma chamber, and the reference voltage is applied to the outer wall.

14. The semiconductor apparatus of claim 1, wherein the reference voltage has a ground potential level.