System and method for testing semiconductor integrated circuit in parallel

• US 20080164894A1
• Filed: 01/03/2008
• Published: 07/10/2008
• Est. Priority Date: 01/04/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Gu, An, Young-Soo, Kim, Jung-Hyeon, Choi, Ho-Jeong
• Application Number:
  US12/006,560
• Publication Number:
  US 20080164894A1
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.

Claims

1. A system for testing semiconductor devices in parallel, comprising:

a probe chuck for loading a plurality of different types of semiconductor DUTs (device under test);

a test head for providing a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs; and

a test controller for controlling the test head and the probe chuck.

2. The system of claim 1, wherein the test head comprises:

a probe card having a needle unit arranged to contact contact pads of the semiconductor DUTs;

a pin board mounted on the probe card for inputting and outputting signals to the needle unit selected by a relay of a switching metric circuit; and

a plurality of source monitor units connected to the pin board for generating and detecting the signals.

3. The system of claim 1, wherein each of the circuit sites comprises a microprocessor.

4. The system of claim 1, wherein different types of test programs are allocated to the circuit sites and run independently.

5. The system of claim 1, wherein, different resources are provided to each of the circuit sites.

6. The system of claim 1, wherein the test controller provides an operator interface for creating a test map.

7. The system of claim 1, wherein each of the semiconductor DUTs is selected from the group consisting of a transistor, a capacitor, and a resistor.

8. The system of claim 1, wherein the semiconductor DUTs are formed on a scribe line disposed between dies on a wafer.

9. A system for testing semiconductor devices in parallel, comprising:

a probe chuck loadable with different types of semiconductor DUTs;

a test head for providing at least two circuit sites that can be used as a single circuit site by combining allocated resources; and

a test controller for controlling the test head and the probe chuck.

10. The system of claim 9, wherein the test head comprises:

a probe card having a needle unit arranged to contact contact pads of the semiconductor DUTs;

a pin board mounted on the probe card for inputting and outputting signals to the needle unit selected by a relay of a switching metric circuit; and

a plurality of source monitor units connected to the pin board for generating and detecting the signals.

11. The system of claim 9, wherein each of the circuit sites comprises a microprocessor.

12. The system of claim 9, wherein different types of test programs are allocated to the circuit sites and run independently

13. The system of claim 9, wherein the test controller provides an operator interface for creating a test map.

14. The system of claim 9, wherein the semiconductor DUTs comprise a flash memory device.

15. The system of claim 9, wherein the semiconductor DUTs are formed on a scribe line disposed between dies on a wafer.

16. A method of testing semiconductor devices in parallel, comprising:

providing a plurality of different types of semiconductor DUTs;

selecting at least two different types of test items;

selecting the different types of semiconductor DUTs arranged at different locations in order to test the test items; and

testing the different types of semiconductor DUTs independently and simultaneously.

17. The method of claim 16, wherein the semiconductor DUTs are test devices formed at a scribe line arranged between dies of a semiconductor substrate.

18. The method of claim 16, wherein, in the testing of the different types of semiconductor DUTs, test resources allocated to the different types of semiconductor DUTs are independently used.

19. The method of claim 16, further comprising combining test resources allocated to the semiconductor DUTs, allocating and using the combined test resources for a large semiconductor DUT when the different types of semiconductor DUTs comprise the large semiconductor DUT requiring expanded test resources.