LEVEL SHIFTER CIRCUIT

• US 20080164931A1
• Filed: 10/17/2007
• Published: 07/10/2008
• Est. Priority Date: 11/22/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: KIMURA, Hiroyuki
• Granted Patent: US 7,501,876 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A level shifter circuit that properly operates even when the power supply voltage is unstable. A level shifter circuit includes a first level shifter unit, a second level shifter unit, and a latch unit. In the first level shifter unit, a transistor is connected to a power supply line to generate drive voltage that is lower than a first power supply voltage. The first level shifter unit outputs complementary signals from the drive voltage. The output of the first level shifter unit is provided to the second level shifter unit. The second level shifter unit converts a complementary signal to a signal having a second power supply voltage. Based on this signal, a signal of the latch unit is switched.

Claims

1. A level shifter circuit comprising:

a first voltage conversion circuit for generating a drive voltage that is lower than a first power supply voltage supplied from the first power supply line and is in correspondence with the first power supply voltage, and generating and outputting complementary signals corresponding to an input signal using the drive voltage;

a second voltage conversion circuit for generating and outputting a signal corresponding to voltages of the complementary signals output from the first voltage conversion circuit using a second power supply voltage supplied from a second power supply line; and

an output latch circuit for performing holding in accordance with the voltage of the signal output from the second voltage conversion circuit.

2. The level shifter circuit according to claim 1, wherein the first voltage conversion circuit includes:

a voltage generation means, connected to the first power supply line, having an operational threshold value for the first power supply voltage; and

a differential amplification circuit for generating the complementary signals corresponding to the input signal and an inverted signal of the input signal using the drive voltage output from the voltage generation means.

3. The level shifter circuit according to claim 2, wherein the voltage generation means includes a first transistor having a gate terminal and drain terminal connected to the first power supply line, and the first transistor has a source terminal connected to the differential amplification circuit of the first voltage conversion circuit to supply the drive voltage.

4. The level shifter circuit according to claim 2, wherein the voltage generation means includes a diode having an anode terminal connected to the first power supply line and a cathode terminal connected to the differential amplification circuit of the first voltage conversion circuit to supply the drive voltage.

5. The level shifter circuit according to claim 2, wherein:

the differential amplification circuit includes a second transistor and a third transistor, each having a source terminal connected to the voltage generation means;

the second transistor has a gate terminal connected to a drain terminal of the third transistor;

the third transistor has a gate terminal connected to a drain terminal of the second transistor;

the drain terminal of the second transistor is connected to a drain terminal of a fourth transistor, the fourth transistor having a gate terminal for receiving the input signal and a source terminal connected to a common line;

the drain terminal of the second transistor is connected to a drain terminal of a fifth transistor, the fifth transistor having a gate terminal for receiving the inverted signal and a source terminal connected to the common line; and

the drain terminals of the fourth and fifth transistors respectively output voltages as the complementary signals provided to the second voltage conversion circuit.

6. The level shifter circuit according to claim 2, wherein:

the differential amplification circuit includes a first inverter element and a second inverter element that are supplied with the drive voltage;

the first inverter element has an input terminal for receiving the input signal;

the first inverter element has an output terminal connected to an input terminal of the second inverter element; and

the first and second inverter elements have output terminals for respectively outputting voltages as the complementary signals provided to the second voltage conversion circuit.

7. The level shifter circuit according to claim 1, wherein:

the second voltage conversion circuit includes a sixth transistor and a seventh transistor, each having a source terminal connected to the second power supply line;

the sixth transistor has a gate terminal connected to a drain terminal of the seventh transistor;

the seventh transistor has a gate terminal connected to a drain terminal of the sixth transistor;

the drain terminal of the sixth transistor is further connected to a drain terminal of an eighth transistor;

the drain terminal of the seventh transistor is further connected to a drain terminal of a ninth transistor;

the eighth and ninth transistors each have a gate terminal connected to the first power supply;

the eighth transistor has a source terminal connected to a drain terminal of a tenth transistor;

the ninth transistor has a source terminal connected to a drain terminal of an eleventh transistor;

the tenth and eleventh transistors each have a source terminal connected to a common line; and

the tenth and eleventh transistors have gate terminals for respectively receiving the complementary signals from the first voltage conversion circuit.

8. The level shifter circuit according to claim 1, wherein:

the second voltage conversion circuit includes a sixth transistor and a seventh transistor, each having a source terminal connected to the second power supply line;

the sixth transistor has a gate terminal connected to a drain terminal of the seventh transistor;

the seventh transistor has a gate terminal connected to a drain terminal of the sixth transistor;

the drain terminal of the sixth transistor is further connected to a drain terminal of a twelfth transistor;

the drain terminal of the seventh transistor is further connected to a drain terminal of a thirteenth transistor;

the twelfth and thirteenth transistors each have a source terminal connected to a drain terminal of a fourteenth transistor;

the fourteenth transistor has a source terminal connected to a common line and a gate terminal connected to the first power supply line; and

the twelfth and thirteenth transistors respectively have gate terminals for receiving the complementary signals from the first voltage conversion circuit.