Interlacing Apparatus, Deinterlacing Apparatus, Display, Image Compressor and Image Decompressor

• US 20080165275A1
• Filed: 05/31/2005
• Published: 07/10/2008
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Jones, Graham R., Hill, Lyndon
• Granted Patent: US 8,102,469 B2
• Time in Patent Office: Days
• US Class Current: 348/446
• CPC Class Codes: H04N 13/15 for colour aspects of image signals
• CPC Class Codes: H04N 13/156 Mixing image signals
• CPC Class Codes: H04N 13/161 Encoding, multiplexing or demultiplexing different image signal components for multi-view video sequence encoding H04N19/597
• CPC Class Codes: H04N 13/31 using parallax barriers
• CPC Class Codes: H04N 19/597 specially adapted for multi-view video sequence encoding

Abstract

An apparatus (24) is provided for interlacing a plurality of input images (I₀, I₁) to form an output image (O). The interlacing apparatus (24) comprises a programmable memory (20) for storing one or more interlacing configuration patterns (P₁, P₂ and P₃) which define a mapping from pixels of the input images (I₀, I₁) to pixels of the output image (O). The interlacing apparatus (24) also comprises a pixel data rearranger or interlacer (16) for rearranging pixel data in accordance with a pattern (P) stored in the memory (20). A pattern controller (18) is provided for selecting any one of the patterns (P₁, P₂ and P₃) for use in the interlacer (16). Such an interlacing apparatus (24) can be used to drive a display device such as a multiple view directional display device or an autostereoscopic display device. A deinterlacer, an image compressor and an image decompressor are also provided.

Claims

1. An apparatus for interlacing a plurality of input images to form an output image, comprising a programmable memory for storing an interlacing configuration pattern (P) defining a mapping from pixels of the input images to pixels of the output image, and a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) stored in the memory, the pattern (P) comprising at least one instruction defining a source or destination image and the position of a source image pixel relative to a destination image pixel.

3. An apparatus as claimed in claim 1, in which the or each input image comprises a sequence of input images and the or each output image comprises a sequence of output images.

4. An apparatus as claimed in claim 1, in which the pixels are colour component pixels.

5. An apparatus as claimed in claim 1, in which the memory is programmed with the pattern (P) during manufacture of the apparatus and is non-reprogrammable.

6. An apparatus as claimed in claim 1, in which the memory is arranged to contain a plurality of patterns and the apparatus comprises a controller for selecting any one of the patterns for use.

7. An apparatus as claimed in claim 6, in which the controller is responsive to an input signal for selecting and reselecting any one of the patterns during operation of the apparatus.

8. An apparatus as claimed in claim 1, in which the memory is reprogrammable for loading or changing the pattern (P) during operation of the apparatus.

9. An apparatus as claimed in claim 1, in which the memory is arranged to be programmed or reprogrammed with the pattern (P) or a fresh pattern by data received with the input image or any of the input images.

11. An apparatus as claimed in claim 1, in which the pattern (P) defines a mapping of a proper subset of input image pixels to a proper subset of output image pixels and the rearranger is arranged to repeat the pattern (P) for a plurality of the proper subsets.

12. An apparatus as claimed in claim 11, in which the rearranger is arranged to repeat the pattern (P) so that the plurality of subsets substantially tiles at least one of the input and output images.

13. An apparatus as claimed in claim 12, in which the plurality of subsets substantially tiles the or each output image.

14. An apparatus as claimed in claim 4, in which the at least one instruction defines a colour component and the position represents the position of a group of source colour component pixels forming a source composite colour group relative to a group of destination colour component pixels forming a destination composite colour group.

15. An apparatus as claimed in claim 1, in which the rearranger is arranged to generate each output image pixel in turn.

16. An apparatus as claimed in claim 1, comprising an input buffer for the or each input image or sequence of input images.

17. An apparatus as claimed in claim 1, comprising an output buffer for the or each output image or sequence of output images.

18. An apparatus as claimed in claim 1, in which the or each output image is built up from a plurality of input images received in sequence.

19. An apparatus as claimed in claim 1, comprising a pixel data processor for processing each pixel data during rearrangement by the rearranger.

20. An apparatus as claimed in claim 1, in which input image data are tagged to indicate to which input image the data relate.

21. A display comprising an apparatus as claimed in claim 1 and a display device.

22. A display as claimed in claim 21, in which the display device is a multiple view directional display device and the rearranger is controlled by the pattern for spatially multiplexing the input images or sequences of input images.

23. A display as claimed in claim 22, in which the display device comprises a spatial light modulator and a parallax optic.

2. An apparatus for deinterlacing an input image to form a plurality of output images, comprising a programmable memory for storing a deinterlacing configuration pattern (P) defining a mapping from pixels of the input image to pixels of the output images, and a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) stored in the memory, the pattern (P) comprising at least one instruction defining a source or destination image and the position of a source image pixel relative to a destination image pixel.

10. An apparatus as claimed in claim 2 in which the memory is arranged to be programmed with the deinterlacing pattern (P) which is derived from an interlacing pattern supplied with the input image or any of the input images.

24. An image compressor comprising a correlation detector for detecting correlation in an input image (I) and establishing therefrom an interlacing configuration pattern (P) defining a mapping from pixels of the input image (I) to pixels of an interlaced image, a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) so as to generate the interlaced image, and a data compressor for compressing the interlaced image.

25. An image decompressor comprising a data decompressor for decompressing a compressed interlaced image (CI) from an image compressor as claimed in claim 24, and a. further pixel data rearranger for rearranging the pixel data of the decompressed interlaced image in accordance with a deinterlacing configuration pattern which is the inverse of the interlacing configuration pattern (P) to provide an output image (I).