Interlacing Apparatus, Deinterlacing Apparatus, Display, Image Compressor and Image Decompressor
First Claim
1. An apparatus for interlacing a plurality of input images to form an output image, comprising a programmable memory for storing an interlacing configuration pattern (P) defining a mapping from pixels of the input images to pixels of the output image, and a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) stored in the memory, the pattern (P) comprising at least one instruction defining a source or destination image and the position of a source image pixel relative to a destination image pixel.
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Abstract
An apparatus (24) is provided for interlacing a plurality of input images (I0, I1) to form an output image (O). The interlacing apparatus (24) comprises a programmable memory (20) for storing one or more interlacing configuration patterns (P1, P2 and P3) which define a mapping from pixels of the input images (I0, I1) to pixels of the output image (O). The interlacing apparatus (24) also comprises a pixel data rearranger or interlacer (16) for rearranging pixel data in accordance with a pattern (P) stored in the memory (20). A pattern controller (18) is provided for selecting any one of the patterns (P1, P2 and P3) for use in the interlacer (16). Such an interlacing apparatus (24) can be used to drive a display device such as a multiple view directional display device or an autostereoscopic display device. A deinterlacer, an image compressor and an image decompressor are also provided.
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Citations
25 Claims
- 1. An apparatus for interlacing a plurality of input images to form an output image, comprising a programmable memory for storing an interlacing configuration pattern (P) defining a mapping from pixels of the input images to pixels of the output image, and a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) stored in the memory, the pattern (P) comprising at least one instruction defining a source or destination image and the position of a source image pixel relative to a destination image pixel.
- 2. An apparatus for deinterlacing an input image to form a plurality of output images, comprising a programmable memory for storing a deinterlacing configuration pattern (P) defining a mapping from pixels of the input image to pixels of the output images, and a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) stored in the memory, the pattern (P) comprising at least one instruction defining a source or destination image and the position of a source image pixel relative to a destination image pixel.
- 24. An image compressor comprising a correlation detector for detecting correlation in an input image (I) and establishing therefrom an interlacing configuration pattern (P) defining a mapping from pixels of the input image (I) to pixels of an interlaced image, a pixel data rearranger for rearranging pixel data in accordance with the pattern (P) so as to generate the interlaced image, and a data compressor for compressing the interlaced image.
Specification