Framebuffer Sharing for Video Processing

• US 20080165287A1
• Filed: 08/30/2007
• Published: 07/10/2008
• Est. Priority Date: 08/30/2006
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Lee, Keith S.K., Doswald, Daniel, Hulyalkar, Samir N.
• Application Number:
  US11/847,802
• Publication Number:
  US 20080165287A1
• Time in Patent Office: Days
• US Class Current: 348/718
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/440263 by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/440281 by altering the temporal resolution, e.g. by frame skipping television signal recording using magnetic recording on tape for reproducing at a rate different from the recording rate H04N5/783
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
• CPC Class Codes: H04N 7/163 by receiver means only

Abstract

An integrated circuit chip configured to be coupled to a single shared memory including, in combination, a memory access module, at least one video signal processing module, and a frame rate converter, wherein the memory access module is configured to coordinate access to the single shared memory by the at least one video signal processing module and the frame rate converter.

Claims

1. An integrated circuit chip configured to be coupled to a single shared memory comprising, in combination:

a memory access module;

at least one video signal processing module; and

a frame rate converter;

wherein the memory access module is configured to coordinate access to the single shared memory by the at least one video signal processing module and the frame rate converter.

2. The chip of claim 1 wherein the at least one video signal processing module and the frame rater converter are configured to share algorithm information.

3. The chip of claim 1 wherein the at least one video signal processing module is configured to store intermediate results in the single shared memory and the frame rater converter is configured to further process the intermediate results using the single shared memory.

4. The chip of claim 1 wherein the at least one video signal processing module comprises a video decoder module.

5. The chip of claim 1 wherein the at least one video signal processing module comprises a deinterlacer.

6. The chip of claim 1 wherein the at least one video signal processing module comprises a scaler.

7. A digital television receiver comprising:

a memory;

a single integrated circuit chip comprising, in combination;

a memory access module;

at least one video signal processing module; and

a frame rate converter;

wherein the memory access module is configured to coordinate access to the memory by the at least one video signal processing module and the frame rate converter.

8. The receiver of claim 7 wherein the at least one video signal processing module and the frame rate converter are configured to share algorithm information.

9. The receiver of claim 7 wherein the at least one video signal processing module is configured to store intermediate results in the memory and the frame rate converter is configured to further process the intermediate results using the memory.

10. The receiver of claim 7 wherein the at least one video signal processing module comprises a video decoder module.

11. The receiver of claim 7 wherein the at least one video signal processing module comprises a deinterlacer.

12. The receiver of claim 7 wherein the at least one video signal processing module comprises a scaler.

13. A method of processing video signals in a receiver, the method comprising:

accessing a single memory from a single integrated circuit chip for use in processing video signals including frame rate conversion of the signals; and

coordinating access to the single memory for frame rate conversion of the video signals and at least one of decoding, deinterlacing, and scaling the video signals.

14. The method of claim 13 further comprising processing the video signals using a single algorithm to perform at least a portion of multiple ones of the decoding, deinterlacing, scaling, and frame rate converting.

15. The method of claim 13 wherein the deinterlacing comprises storing intermediate results to the single memory and the frame rate converting comprises using the intermediate results.

16. The method of claim 13 wherein the decoding comprises storing intermediate results to the single memory and the frame rate converting comprises using the intermediate results.