eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP

• US 20080165601A1
• Filed: 01/05/2007
• Published: 07/10/2008
• Est. Priority Date: 01/05/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Schuster, Stanley E., Matick, Richard E.
• Granted Patent: US 7,460,387 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.

Claims

1. A DRAM memory array comprising:

a plurality of memory cells, each of said plurality of memory cells further comprising;

a device, each of said plurality of memory cells having one of said device organized in a row representing a plurality of word lines or a bit column representing bits of said plurality of word lines, each said bit column having more than one pair of a local bit line true, and a local bit line complement, said local bit line true and said local bit line complement are balanced, said local bit line true is connected by way of a first CMOS transistor switch to a global bit line true and said local bit line complement is connected by way of a second CMOS transistor switch to a global bit line complement, said global bit line true and said global bit line complement are balanced.

2. The DRAM memory array in accordance with claim 1, wherein said device is a transistor, CMOS transistor, nFET, or pFET.

3. The DRAM memory array in accordance with claim 1, wherein said DRAM memory array further comprising:

a first stage differential sense amplifier, said first stage differential sense amplifier having a cross coupled differential half latch connected to each of said local bit line true and said local bit line complement, said first stage differential sense amplifier being responsive to a first timing pulse effectuating the setting of said first stage differential sense amplifier.

4. The DRAM memory array in accordance with claim 3, wherein said DRAM memory array further comprising:

a second stage global sense amplifier, said second stage global sense amplifier having a full cross coupled latch connected to each of said global bit line true and said global bit line complement, said second stage global sense amplifier being responsive to a plurality of global timing pulses effectuating the setting of said second stage global sense amplifier.

5. The DRAM memory array in accordance with claim 4, wherein data access of said DRAM memory array is performed as follows:

at start of data access, said plurality of word lines are ‘

LOW’

or ‘

OFF’

, said local bit line true, said local bit line complement, said global bit line true, and said global bit line complement are charged to approximately one-half power supply voltage, said first CMOS transistor switch and said second CMOS transistor switch are ‘

ON’

, and said first stage differential sense amplifier and said second stage global sense amplifier are ‘

OFF’

;

next said first CMOS transistor switch and said second CMOS transistor switch are switched ‘

OFF’

, accessed said plurality of word lines transition ‘

HIGH’

turning ‘

ON’

an access transistor between a first cell storage capacitor associated with said local bit line true or a second cell storage capacitor associated with said local bit line complement;

next a differential voltage is developed across said local bit line true and said local bit line complement resultant from accessed said plurality of memory cells being turned ‘

ON’

;

next said first timing pulse transitions effectuating the setting of said first stage differential sense amplifier;

next said first CMOS transistor switch and said second CMOS transistor switch are switched ‘

ON’

; and

next said plurality of global timing pulses transition effectuating the setting of said second stage global sense amplifier, wherein a full power supply voltage appears across said local bit line true and said local bit line complement.

6. The DRAM memory array in accordance with claim 5, wherein said first stage differential sense amplifier is immune to common mode noise.

7. The DRAM memory array in accordance with claim 6, wherein said second stage global sense amplifier is immune to common mode noise.

8. A method of data accessing a DRAM memory array, said method comprising:

initializing data access, said DRAM memory array comprising a plurality of memory cells, each of said plurality of memory cells further comprising;

a device, each of said plurality of memory cells having one of said device organized in a row representing a plurality of word lines or a bit column representing bits of said plurality of word lines, each said bit column having more than one pair of a local bit line true, and a local bit line complement, said local bit line true and said local bit line complement are balanced, said local bit line true is connected by way of a first CMOS transistor switch to a global bit line true and said local bit line complement is connected by way of a second CMOS transistor switch to a global bit line complement, said global bit line true and said global bit line complement are balanced;

a first stage differential sense amplifier, said first stage differential sense amplifier having a cross coupled differential half latch connected to each of said local bit line true and said local bit line complement, said first stage differential sense amplifier being responsive to said first timing pulse effectuating the setting of said first stage differential sense amplifier;

a second stage global sense amplifier, said second stage global sense amplifier having a full cross coupled latch connected to each of said global bit line true and said global bit line complement, said second stage global sense amplifier being responsive to a global timing pulse effectuating the setting of said second stage global sense amplifier; and

said plurality of word lines are ‘

LOW’

or ‘

OFF’

, said local bit line true, said local bit line complement, said global bit line true, and said global bit line complement are charged to approximately one-half power supply voltage, said first CMOS transistor switch and said second CMOS transistor switch are ‘

ON’

, and said first stage differential sense amplifier and said second stage global sense amplifier are ‘

OFF’

;

switching said first CMOS transistor switch and said second CMOS transistor switch are switched ‘

OFF’

, accessed said plurality of word lines transition ‘

HIGH’

turning ‘

ON’

an access transistor between a first cell storage capacitor associated with said local bit line true or a second cell storage capacitor associated with said local bit line complement;

developing a differential voltage across said local bit line true and said local bit line complement resultant from accessed said plurality of memory cells being turned ‘

ON’

;

transitioning said first timing pulse effectuating the setting of said first stage differential sense amplifier;

switching said first CMOS transistor switch and said second CMOS transistor switch ‘

ON’

; and

transitioning said global timing pulse effectuating the setting of said second stage global sense amplifier, wherein a full power supply voltage appears across said local bit line true and said local bit line complement.

9. The method in accordance with claim 8, wherein said first stage differential sense amplifier is immune to common mode noise.

10. The method in accordance with claim 9, wherein said second stage global sense amplifier is immune to common mode noise.