Hardware-based beacon processing

• US 20080165769A1
• Filed: 01/08/2007
• Published: 07/10/2008
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Nordic Semiconductor ASA
• Original Assignee: Hellosoft Incorporated (Imagination Technologies Group Ltd.)
• Inventors: Barman, Kaushik, Malladi, Raghavendra, Aldaz, Luis, Johnson, Allan A.
• Granted Patent: US 8,238,278 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller

Abstract

Hardware-based beacon processing. A hardware-centric medium access control (MAC) device includes a packet receiver and a beacon processor. The packet receiver receives a plurality of packets comprising at least one beacon packet. The beacon processor receives packets of the plurality of packets and filters out unwanted packets of the plurality of packets without requiring the use of other components of the hardware-centric MAC device and without requiring the use of a microprocessor.

Claims

1. A hardware-centric medium access control (MAC) device comprising:

a packet receiver for receiving a plurality of packets comprising at least one beacon packet; and

a beacon processor for receiving packets of said plurality of packets for filtering out unwanted packets of said plurality of packets without requiring the use of other components of said hardware-centric MAC device and without requiring the use of a microprocessor.

2. The hardware-centric MAC device as recited in claim 1 wherein said packet receiver and said beacon processor are hardware devices.

3. The hardware-centric MAC device as recited in claim 1 wherein said beacon processor is operable to deactivate after processing a packet and to activate in advance of receipt of a packet.

4. The hardware-centric MAC device as recited in claim 3 wherein said beacon processor is operable to reactivate prior to receipt of a packet by a time at least long enough to account for clock drift.

5. The hardware-centric MAC device as recited in claim 1 wherein said packet receiver and said beacon processor are comprised within a hardware media access plane module of said hardware-centric MAC device, said hardware media access plane module for performing real-time data communication functions independent of a microprocessor.

6. The hardware-centric MAC device as recited in claim 5 further comprising a control plane module communicatively coupled to said hardware media access plane module, said control plane module for providing control functions of said hardware-centric MAC device.

7. The hardware-centric MAC device as recited in claim 5 wherein said hardware media access plane module is implemented in gate logic, such that real-timing requirements of said hardware-centric MAC device are handled in gate logic.

8. An apparatus comprising:

a microprocessor;

a memory communicatively coupled to said microprocessor;

a wireless communication module communicatively coupled to said microprocessor, said wireless communication module for receiving and transmitting voice traffic over a wireless connection and comprising;

an analog to digital converter (ADC)/digital to analog converter (DAC) interface comprising a phase-locked loop (PLL), said ADC/DAC interface for receiving a packet;

a physical layer (PHY) device for decoding at least a portion of said packet; and

a hardware-centric medium access control (MAC) device communicatively coupled to said PHY device, wherein said hardware-centric MAC device is configured to perform beacon processing without requiring use of said microprocessor.

9. The apparatus as recited in claim 8 wherein said hardware-centric MAC device comprises:

a packet receiver for receiving at least one beacon packet; and

a beacon processing module for receiving said packet and for performing beacon processing of said packet by determining whether said packet is a beacon packet and filtering out packets that are not beacon packets.

10. The apparatus as recited in claim 9 wherein said packet receiver and said beacon processing module are hardware devices.

11. The apparatus as recited in claim 9 wherein said beacon processing module, said ADC/DAC interface and said PHY device are deactivated after processing said packet and operable to activate in advance of receipt of a subsequent packet.

12. The apparatus as recited in claim 11 wherein said beacon processing module, said ADC/DAC interface and said PHY device are operable to reactivate prior to receipt of a packet by a time at least long enough to account for clock drift.

13. The apparatus as recited in claim 8 wherein said packet receiver and said beacon processing module are comprised within a hardware media access plane module of said hardware-centric MAC device, said hardware media access plane module for performing real-time data communication functions independent of said microprocessor.

14. The apparatus as recited in claim 13 wherein said hardware-centric MAC device further comprises a control plane module communicatively coupled to said hardware media access plane module, said control plane module for providing control functions of said hardware-centric MAC device.

15. The apparatus as recited in claim 13 wherein said hardware media access plane module is implemented in gate logic, such that real-timing requirements of said hardware-centric MAC device are handled in gate logic.

16. A method comprising:

receiving at least one packet at a hardware beacon processing module, wherein said hardware beacon processing module is operable without requiring use of a microprocessor;

determining whether said packet is a beacon packet; and

processing said packet by filtering out said packet if said packet is not a beacon packet.

17. The method as recited in claim 16 wherein said hardware beacon processing module is comprised within a hardware-centric medium access control (MAC) device.

18. The method as recited in claim 17 further comprising:

if said packet is a beacon packet, activating at least a portion of said hardware-centric MAC device; and

processing said beacon packet at said at said portion of said hardware-centric MAC device.

19. The method as recited in claim 16 further comprising:

deactivating said hardware beacon processing module after processing said packet; and

activating said hardware beacon processing module prior to receiving a subsequent packet.

20. The method as recited in claim 19 wherein said activating comprises activating said hardware beacon processing module by a time at least long enough to account for clock drift.