METHOD OF MANUFACTURE FOR A SEMICONDUCTOR DEVICE

• US 20080166845A1
• Filed: 01/08/2008
• Published: 07/10/2008
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Granted Patent: US 8,420,483 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming one or more insulator layers on the semiconductor layer of the second conductivity type;

etching a plurality of trenches in the semiconductor layer of the second conductivity type, thereby forming a portion of a plurality of CC trenches and a CG trench;

forming an oxide layer in the plurality of trenches and on the semiconductor layer of the second conductivity type;

forming a masking layer on a portion of the one or more insulating layers;

forming a gate oxide layer in the CG trench;

forming polysilicon gate material in the CG trench;

forming a second insulator layer, thereby filling a portion of the CC trenches;

forming a second material, thereby filling a second portion of the CC trenches;

forming a third insulator layer, thereby filling a remainder of the CC trenches;

forming one or more device regions; and

forming a source metal layer.

2. The method of claim 1 wherein the semiconductor layer of the first conductivity type comprises an n+ silicon substrate doped with at least one of phosphorus, antimony, or arsenic.

3. The method of claim 1 wherein the semiconductor layer of the second conductivity type comprises a multi-layer structure including an n-type material layer on the semiconductor layer of the first conductivity type and a p-type material layer on the n-type material layer.

4. The method of claim 1 further comprising:

forming a second oxide layer over the polysilicon gate material; and

patterning the second oxide layer; and

5. The method of claim 1 further comprising performing an etching process to extend a depth of the plurality of CC trenches.

6. The method of claim 1 wherein the second material comprises aluminum fluoride.

7. The method of claim 6 wherein the second material further comprises an insulating layer.

8. The method of claim 6 further comprising:

not forming a second insulator layer; and

continuing the deposition of the second material, thereby filling the remainder of the CC trenches.

9. The method of claim 1 wherein etching the plurality of trenches in the semiconductor layer of the second conductivity type is performed concurrently.

10. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming an insulator layer on the semiconductor layer of the second conductivity type;

etching a trench into at least the semiconductor layer of the second conductivity type;

forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type;

implanting ions into the thermal oxide layer;

forming a second insulator layer, thereby filling at least a portion of the trench;

removing the second insulator layer from a portion of the trench;

forming an oxide layer in the trench and on the epitaxial layer;

forming a material in the trench;

forming one or more device regions;

forming a third insulating layer over the material;

patterning the third insulating layer; and

forming a source metal layer.

11. The method of claim 10 wherein the semiconductor layer of the first conductivity type comprises an n+ doped substrate doped with at least one of phosphorus, antimony, or arsenic.

12. The method of claim 10 wherein the semiconductor layer of the second conductivity type comprises a multi-layer structure including an n-type material layer on the semiconductor layer of the first conductivity type and a p-type material layer on the n-type material layer.

13. The method of claim 10 wherein the semiconductor layer of the second conductivity type comprises an n-type material layer on the semiconductor layer of the first conductivity type.

14. The method of claim 10 wherein the trench extends to the semiconductor layer of the first conductivity type.

15. The method of claim 10 wherein the ions comprise cesium ions.

16. The method of claim 15 further comprising:

capping the second insulator layer; and

performing a thermal treatment to anneal the cesium ions.

17. The method of claim 10 wherein the ions comprise iodine, bromine, chromium, aluminum, or chlorine ions.

18. The method of claim 17 further comprising:

capping the second insulator layer; and

performing a thermal treatment to anneal the iodine, bromine, chromium, aluminum, or chlorine ions.

19. The method of claim 10 further comprising:

thinning the semiconductor layer of the first conductivity type; and

forming a drain metal layer.

20. The method of claim 10 wherein the material comprises polysilicon.

21. The method of claim 10 wherein the second insulator layer comprises a multilayer dielectric stack.

22. The method of claim 21 wherein the multilayer dielectric stack comprises:

a layer of silicon oxide;

a layer of silicon nitride; and

a second layer of silicon oxide.

23. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

etching a trench into at least the semiconductor layer of the second conductivity type;

forming a first insulator layer in the trench;

forming a second insulator layer, thereby filling at least a portion of the CC trenches;

forming a gate material in the trench;

forming one or more device regions; and

forming a source metal layer.

24. The method of claim 23 wherein the first insulator layer and the second insulator layer comprise silicon oxide.

25. The method of claim 23 wherein the second insulator layer comprises aluminum fluoride.

26. The method of claim 23 further comprising forming a third insulator layer after forming the second insulator layer and prior to forming the gate material.

27. The method of claim 26 wherein the third insulator layer comprises a thermal silicon oxide.

28. The method of claim 23 wherein the gate material comprises polysilicon.

29. The method of claim 23 wherein the semiconductor layer of the first conductivity type comprises an n+ silicon substrate doped with at least one of phosphorus, antimony, or arsenic.

30. The method of claim 23 wherein the semiconductor layer of the second conductivity type comprises a multi-layer structure including an n-type material layer on the semiconductor layer of the first conductivity type.

31. The method of claim 23 further comprising:

forming a second oxide layer over the polysilicon gate material; and

patterning the second oxide layer.

32. The method of claim 23 further comprising performing an etching process to extend a depth of the plurality of CC trenches.

33. The method of claim 23 wherein the trench extends into the semiconductor layer of the first conductivity type.

34. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming an insulator layer on the semiconductor layer of the second conductivity type;

etching one or more trenches into at least the semiconductor layer of the second conductivity type;

forming a second insulator layer in the one or more trenches;

implanting ions into the second insulator layer;

forming a third insulator layer, thereby filling at least a portion of the one or more trenches;

etching an additional trench into at least the semiconductor layer of the second conductivity type;

forming a gate oxide layer in the additional trench;

forming a gate material in the additional trench;

forming one or more device regions; and

forming a source metal layer.

35. The method of claim 34 further comprising:

forming a second oxide layer over the gate material; and

patterning the second oxide layer prior to forming the source metal layer.

36. The method of claim 34 further comprising:

thinning the semiconductor layer of the first conductivity type; and

forming a drain metal layer.

37. The method of claim 34 wherein the semiconductor layer of a first conductivity type comprises an n+ doped substrate doped with at least one of phosphorus, antimony, or arsenic.

38. The method of claim 37 wherein the semiconductor layer of the first conductivity type comprises an n-type material layer.

39. The method of claim 37 wherein the ions comprise iodine, bromine, chromium, aluminum, or chlorine ions.

40. The method of claim 39 further comprising performing a thermal treatment to anneal the iodine, bromine, chromium, aluminum, or chlorine ions.

41. The method of claim 34 wherein the semiconductor layer of the first conductivity type comprises a p+ doped substrate.

42. The method of claim 41 wherein the semiconductor layer of the first conductivity type comprises a p-type material layer.

43. The method of claim 41 wherein the ions comprise cesium ions.

44. The method of claim 43 further comprising performing a thermal treatment to anneal the cesium ions.

45. The method of claim 34 wherein the one or more trenches extend to the semiconductor layer of the first conductivity type.

46. The method of claim 34 wherein the second insulator layer comprises a thermal oxide layer.

47. The method of claim 34 wherein forming a third insulator layer completely fills the one or more trenches.

48. The method of claim 34 wherein the insulator layer comprises a multilayer dielectric stack.

49. The method of claim 48 wherein the multilayer dielectric stack comprises:

a layer of silicon oxide; and

a layer of silicon nitride.

50. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming an insulator layer on the semiconductor layer of the second conductivity type;

etching a trench into at least the semiconductor layer of the second conductivity type;

forming an oxide layer in the trench and on the semiconductor layer of the second conductivity type;

implanting ions into the oxide layer;

forming a second insulator layer, thereby filling the trench;

forming one or more device regions; and

forming a metal layer.

51. The method of claim 50 wherein the trench extends to the semiconductor layer of the first conductivity type.

52. The method of claim 50 wherein the ions comprise cesium ions.

53. The method of claim 52 further comprising:

capping the second insulator layer; and

performing a thermal treatment to anneal the cesium ions.

54. The method of claim 50 wherein the ions comprise iodine, bromine, chromium, aluminum, or chlorine ions.

55. The method of claim 54 further comprising:

capping the second insulator layer; and

performing a thermal treatment to anneal the iodine, bromine, chromium, aluminum, or chlorine ions.

56. The method of claim 50 wherein the second insulator layer comprises a multilayer dielectric stack.