Methods of Forming Recessed Access Devices Associated With Semiconductor Constructions

• US 20080166856A1
• Filed: 03/19/2008
• Published: 07/10/2008
• Est. Priority Date: 03/25/2005
• Status: Active Grant

• Current Assignee: Jigish D. Trivedi, John K. Zahurak, Kunal R. Parekh, Sanh D. Tang, Suraj Mathew
• Original Assignee: Jigish D. Trivedi, John K. Zahurak, Kunal R. Parekh, Sanh D. Tang, Suraj Mathew
• Inventors: Tang, Sanh D., Mathew, Suraj, Trivedi, Jigish D., Parekh, Kunal R., Zahurak, John K.
• Granted Patent: US 7,897,460 B2
• Time in Patent Office: Days
• US Class Current: 438/435
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

Claims

1-30. -30. (canceled)

31. :

A method of forming recessed access devices associated with a semiconductor construction, comprising;

providing a semiconductor substrate comprising monocrystalline silicon;

forming recessed access device trenches within the monocrystalline silicon of the substrate;

filling the recessed access device trenches with a first electrically insulative material;

patterning the first electrically insulative material into a mask defining a plurality of access device regions, the access device regions being islands surrounded by an isolation region;

the access device regions comprising only portions of the recessed access device trenches;

etching into the monocrystalline silicon of the substrate within said isolation region to form at least one cavity within the monocrystalline silicon and extending around the access device regions;

filling the at least one cavity with a second electrically insulative material;

removing at least the majority of the first electrically insulative material while leaving the second electrically insulative material within the at least one cavity; and

after removing at least the majority of the first electrically insulative material, forming gate material within the portions of the recessed access device trenches comprised by the access device regions.

32. :

The method of claim 31 wherein the first electrically insulative material comprises a silicon-nitride-containing layer over a silicon-dioxide-containing layer.

33. :

The method of claim 32 wherein the removing at least the majority of the first electrically insulative material removes both the silicon-nitride-containing layer and the silicon-dioxide-containing layer.

34. :

The method of claim 31 wherein the access device regions are substantially elliptical;

wherein the substantially elliptical access device regions have primary longitudinal elliptical axes;

wherein the recessed access device trenches have primary length axes; and

wherein the primary longitudinal elliptical axes of the substantially elliptical access device regions are substantially orthogonal to the primary length axes of the recessed access device trenches.

35. :

The method of claim 31 wherein the access device regions are substantially elliptical;

wherein the substantially elliptical access device regions have primary longitudinal elliptical axes;

wherein the recessed access device trenches have primary length axes; and

wherein the primary longitudinal elliptical axes of the substantially elliptical access device regions are not substantially orthogonal to the primary length axes of the recessed access device trenches.

36. :

The method of claim 31 wherein the at least one cavity extends to a depth in the monocrystalline silicon that is at least twice as large as a depth to which the recessed access device trenches extend into the monocrystalline silicon.

37. :

A method of forming recessed access devices associated with a semiconductor construction, comprising;

forming recessed access device trenches extending into a semiconductor substrate;

depositing gate material within the recessed access device trenches;

forming a first electrically insulative material over the gate material;

patterning the first electrically insulative material into a mask defining a plurality of access device regions, the access device regions being islands surrounded by isolation region;

the access device regions comprising only portions of the recessed access device trenches;

etching into the substrate of said isolation region to recess the substrate of said isolation region, the etching also removing the gate material from between the access device regions while leaving the gate material within the access device regions;

covering the recessed substrate with a second electrically insulative material to cover the isolation region with the second electrically insulative material;

removing the first electrically insulative material; and

after removing the first electrically insulative material, forming a plurality of conductive lines, individual conductive lines extending across multiple access device regions and electrically interconnecting gate material of the multiple access device regions with one another.

38. :

The method of claim 37 wherein the depositing the gate material fills the recessed access device trenches with the gate material and forms the gate material in regions outside of the recessed access device trenches, and further comprising planarizing the gate material to remove the gate material from the regions outside of the recessed access device trenches while leaving the gate material within the recessed access device trenches.

39. :

The method of claim 38 wherein the gate material comprises silicon and is conductively-doped prior to the planarizing.

40. :

The method of claim 38 wherein the gate material comprises silicon and is not conductively-doped prior to the planarizing.

41. :

The method of claim 37 wherein;

the substrate comprises monocrystalline silicon;

the forming the recessed access device trenches etches into the monocrystalline silicon to a first depth; and

the etching into the substrate of said isolation region etches into the monocrystalline of the substrate to a second depth that is at least two-fold greater than the first depth.

42. :

The method of claim 37 further comprising removing at least substantially all of the first electrically insulative material prior to forming the conductive lines.