Conditional activation and deactivation of a microprocessor

• US 20080168189A1
• Filed: 01/08/2007
• Published: 07/10/2008
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Nordic Semiconductor ASA
• Original Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Inventors: Barman, Kaushik, Wagner, John P., Aldaz, Luis, Johnson, Allan A., Malladi, Raghavendra
• Granted Patent: US 9,760,146 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Conditional activation and deactivation of a microprocessor. A hardware portion of an apparatus performs packet processing on received data, where the hardware portion selectively decodes the received data. A microprocessor performs data processing on decoded data, where the microprocessor is conditionally activated for performing the data processing and is conditionally deactivated when not performing the data processing. An output portion receives processed data and audibly renders the processed data without requiring the microprocessor.

Claims

1. An apparatus comprising:

a hardware portion for performing packet processing on received data, said hardware portion for selectively decoding said received data;

a microprocessor for performing data processing on decoded data, wherein said microprocessor is conditionally activated for performing said data processing and is conditionally deactivated when not performing said data processing; and

an output portion for receiving processed data and for audibly rendering said processed data without requiring said microprocessor.

2. The apparatus of claim 1 wherein said output portion comprises:

a buffer for receiving and buffering said processed data; and

a media output for accessing said processed data from said buffer and for audibly rendering said processed data.

3. The apparatus of claim 1 wherein said microprocessor is not activated when performing said data processing if said decoded data is voice data.

4. The apparatus of claim 1 wherein said microprocessor is activated when not performing said data processing if said microprocessor is executing at least one application running on said apparatus.

5. The apparatus of claim 1 wherein said microprocessor is operable to provide dynamic clock scaling such that said microprocessor performs data processing at a frequency based at least in part on data processing requirements of said decoded data.

6. The apparatus of claim 4 wherein said microprocessor is operable to provide dynamic clock scaling such that said microprocessor executes at least one said application at a frequency based at least in part on processing requirements of said application.

7. The apparatus of claim 1 wherein said hardware portion comprises a hardware-centric medium access control (MAC) device for performing said packet processing on said received data without requiring said microprocessor.

8. An apparatus comprising:

a hardware portion for performing packet processing on received data, said hardware portion for selectively decoding said received data, said hardware portion comprising;

a physical layer (PHY) device; and

a hardware-centric medium access control (MAC) device communicatively coupled to said PHY device, wherein said MAC device is configured to perform real-time voice communication functions without requiring a microprocessor;

a data processing portion for performing data processing on decoded data, said data processing portion comprising said microprocessor, wherein said microprocessor is conditionally activated for performing said data processing and is conditionally deactivated when not performing said data processing; and

a buffered media output for receiving processed data and for audibly rendering said processed data without requiring said microprocessor.

9. The apparatus of claim 8 wherein said buffered media output comprises:

a buffer for receiving and buffering said processed data; and

a media output for accessing said processed data from said buffer and for audibly rendering said processed data.

10. The apparatus of claim 8 wherein said microprocessor is not activated when performing said data processing if said decoded data is voice data.

11. The apparatus of claim 8 wherein said microprocessor is activated when not performing said data processing if said microprocessor is executing at least one application running on said apparatus.

12. The apparatus of claim 8 wherein said microprocessor is operable to provide dynamic clock scaling such that said microprocessor performs data processing at a frequency based at least in part on data processing requirements of said decoded data.

13. The apparatus of claim 11 wherein said microprocessor is operable to provide dynamic clock scaling such that said microprocessor executes at least one said application at a frequency based at least in part on processing requirements of said application.

14. The apparatus of claim 8 wherein said hardware portion further comprises:

an activity sensor device for sensing a packet; and

a MAC address parser for receiving said packet, for processing a header of said packet, and for activating said hardware-centric MAC device in response to recognizing a MAC address within said header, such that said hardware-centric MAC device is not activated if said MAC address parser does not recognize said MAC address.

15. A method for selectively deactivating a microprocessor, said method comprising:

performing packet processing on received data at a hardware portion of an electronic device;

selectively decoding said received data;

performing data processing on decoded data, wherein said microprocessor is conditionally activated for performing said data processing; and

conditionally deactivating said microprocessor after performing said data processing if said microprocessor is not executing an application running on said electronic device.

16. The method as recited in claim 15 wherein said performing packet processing comprises performing real-time voice communication functions without requiring said microprocessor using a hardware-centric medium access control (MAC) device of said electronic device.

17. The method as recited in claim 16 wherein said performing packet processing comprises performing address matching comprising:

decoding at least a header portion of a packet of said received data, said header portion including a destination MAC address;

determining whether said MAC address of said packet is recognized; and

responsive to recognizing said MAC address, activating said MAC device for performing packet processing functions.

18. The method as recited in claim 15 further comprising:

buffering processed data; and

audibly rendering said processed data at a media output.

19. The method of claim 15 further comprising dynamically scaling an operating frequency of said microprocessor such that said microprocessor operates at a frequency based at least in part on processing requirements of said decoded data.

20. The method of claim 15 further comprising dynamically scaling an operating frequency of said microprocessor such that said microprocessor operates at a frequency based at least in part on processing requirements of said application.