Barrier and Interrupt Mechanism for High Latency and Out of Order DMA Device

• US 20080168191A1
• Filed: 01/10/2007
• Published: 07/10/2008
• Est. Priority Date: 01/10/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Torre, Luis E. De la, Biran, Giora, Nicholas, Richard, Drerup, Bernard C., Gupta, Jyoti
• Granted Patent: US 7,603,490 B2
• Time in Patent Office: Days
• US Class Current: 710/23
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possible. Certain descriptors are defined to be “barrier descriptors.” When the DMA device encounters a barrier descriptor, it ensures that all of the previous descriptors complete before the barrier descriptor completes. The DMA device further ensures that any interrupt generated by a barrier descriptor will not assert until the data move associated with the barrier descriptor completes. The DMA controller only permits interrupts to be generated by barrier descriptors. The barrier descriptor concept also allows software to embed mailbox completion messages into the scatter/gather linked list of descriptors.

Claims

1. A method for performing a direct memory access block move in a direct memory access device, the method comprising:

receiving a direct memory access block move descriptor, wherein the direct memory access block move descriptor indicates a source and a target and wherein the direct memory access block move descriptor is identified as a barrier descriptor;

converting the direct memory access block move descriptor into one or more direct memory access requests for the direct memory access block move descriptor;

identifying a last direct memory access request within the one or more direct memory access requests; and

processing the one or more direct memory access requests to satisfy the direct memory access block move request such that the direct memory access device does not process the last direct memory access request before all other direct memory access requests within the one or more direct memory access requests are processed.

2. The method of claim 1, further comprising:

setting a barrier attribute associated with the last direct memory access request.

3. The method of claim 1, further comprising:

toggling a barrier tag each time a barrier descriptor is processed.

4. The method of claim 1, further comprising:

responsive to completion of the last direct memory access request, generating an interrupt.

5. The method of claim 1, wherein the last direct memory access request is configured to move a completion code to a mailbox.

6. A method in a direct memory access engine in a direct memory access device for performing a direct memory access block move, the method comprising:

receiving a direct memory access block move descriptor, wherein the direct memory access block move descriptor indicates a source and a target and wherein the direct memory access block move request is identified as a barrier descriptor;

converting the direct memory access block move descriptor into one or more direct memory access requests for the direct memory access block move descriptor;

identifying a last direct memory access request within the one or more direct memory access requests;

setting a barrier attribute associated with the last direct memory access request; and

for each given direct memory access request in the one or more direct memory access requests;

determining whether the barrier attribute is set for the given direct memory access request;

if the barrier attribute is set, determining whether a barrier is pending for a channel associated with the given direct memory access request; and

if a barrier is not pending for the channel associated with the given direct memory access request, issuing the given direct memory access request to a bus engine in the direct memory access device.

7. The method of claim 6, further comprising:

if the barrier attribute is not set for the given direct memory access request, issuing the given direct memory access to the bus engine.

8. The method of claim 6, further comprising:

if a barrier is pending for the channel associated with the given direct memory access request, holding the given direct memory access request until a barrier clear signal is received from the bus engine for the channel associated with the given direct memory access request.

9. The method of claim 6, further comprising:

responsive to issuing the given direct memory access request to the bus engine, toggling a barrier tag, such that direct memory access requests on a first side of the barrier have a barrier tag set to a first value and direct memory requests on a second side of the barrier have a barrier tag set to a second value.

10. The method of claim 6, wherein the direct memory access block move descriptor has an interrupt bit set, the method further comprising:

setting an interrupt bit associated with the last direct memory access request.

11. A method in a bus engine in a direct memory access device for performing a direct memory access block move, the method comprising:

receiving a direct memory access request from a direct memory access queue;

determining whether the direct memory access request has a barrier attribute set;

if the direct memory access request has a barrier attribute set, determining whether all direct memory access requests before the barrier have completed; and

if all direct memory access requests before the barrier have not completed, holding the direct memory access request from completing.

12. The method of claim 11, further comprising:

if the direct memory access request is after the barrier and does not have a barrier attribute set, issuing a direct memory access transaction for the direct memory access request.

13. The method of claim 11, further comprising:

if the direct memory access request is before the barrier and does not have a barrier attribute set, issuing a direct memory access transaction for the direct memory access request.

14. The method of claim 13, further comprising:

responsive to issuing the direct memory access transaction, determining whether all direct memory access requests before the barrier without the barrier attribute being set have completed;

if all direct memory access requests before the barrier without the barrier attribute being set have completed, determining whether a barrier direct memory access request with the barrier attribute set is being held from completing; and

if a barrier direct memory access request with the barrier attribute set is being held from completing, issuing a direct memory access transaction for the barrier direct memory access request.

15. The method of claim 14, further comprising:

responsive to issuing the direct memory transaction for the barrier direct memory request, determining whether an interrupt bit is set for the barrier direct memory request; and

if an interrupt bit is set for the barrier direct memory access request, generating an interrupt.

16. A direct memory access device, comprising:

a direct memory access engine, wherein the direct memory access engine is configured to;

receive a direct memory access block move descriptor, wherein the direct memory access block move descriptor indicates a source and a target and wherein the direct memory access block move request is identified as a barrier descriptor;

convert the direct memory access block move descriptor into one or more direct memory access requests for the direct memory access block move descriptor;

identify a last direct memory access request within the one or more direct memory access requests;

set a barrier attribute associated with the last direct memory access request; and

issue the one or more direct memory access requests to a direct memory access queue; and

a bus engine, wherein the bus engine is configured to;

receive a direct memory access request from a direct memory access queue;

determine whether the direct memory access request has a barrier attribute set;

if the direct memory access request has a barrier attribute set, determine whether all direct memory access requests before the barrier have completed; and

if all direct memory access requests before the barrier have not completed, hold the direct memory access request from completing.

17. The direct memory access device of claim 16, wherein the direct memory access engine is further configured to:

if a barrier is pending for the channel associated with a given direct memory access request, hold the given direct memory access request until a barrier clear signal is received from the bus engine for the channel associated with the given direct memory access request.

18. The direct memory access device of claim 16, wherein the direct memory access engine is further configured to:

responsive to issuing a given direct memory access request to the bus engine, toggle a barrier tag, such that direct memory access requests on a first side of the barrier have a barrier tag set to a first value and direct memory requests on a second side of the barrier have a barrier tag set to a second value.

19. The direct memory access device of claim 16, wherein the bus engine is further configured to:

if the direct memory access request is before the barrier and does not have a barrier attribute set, issue a direct memory access transaction for the direct memory access request.

20. The direct memory access device of claim 19, wherein the bus engine is further configured to:

responsive to issuing the direct memory access transaction, determine whether all direct memory access requests before the barrier without the barrier attribute being set have completed;

if all direct memory access requests before the barrier without the barrier attribute being set have completed, determine whether a barrier direct memory access request with the barrier attribute set is being held from completing; and

if a barrier direct memory access request with the barrier attribute set is being held from completing, issue a direct memory access transaction for the barrier direct memory access request.