Method and Apparatus for Self-Healing Symmetric Multi-Processor System Interconnects

• US 20080168255A1
• Filed: 01/09/2007
• Published: 07/10/2008
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McLaughlin, Mark David, Yanez, Jorge N., Abou-Emara, Luai A.
• Granted Patent: US 7,661,006 B2
• Time in Patent Office: Days
• US Class Current: 712/28
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

Claims

1. A computer implemented method for managing symmetric multiprocessor interconnects, the computer implemented method comprising:

identifying functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections;

mapping every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections to form an interconnect matrix;

creating a path map using the interconnect matrix, wherein the path map comprises a sequence of communication connections between the plurality of processors; and

initializing the plurality of processors using the path map.

2. The computer implemented method of claim 1 further comprising:

responsive to identifying a failed connection, removing the failed connection from the interconnect matrix, wherein a failed connection is a connection between two processors in the plurality of processors that has failed.

3. The computer implemented method of claim 1 further comprising:

storing the identified functional communication connections in an output file.

4. The computer implemented method of claim 2 wherein removing the failed connection from the interconnect matrix forms an updated interconnect matrix, and further comprising:

responsive to a determination that the failed connection is a connection in the path map, generating an alternative path map based on the updated interconnect matrix, wherein the alternative path map bypasses the failed connection.

5. The computer implemented method of claim 4 wherein the failed connection is a connection that failed during initialization, and further comprising:

continuing initialization of the plurality of processors in accordance with the alternative path map.

6. The computer implemented method of claim 4 wherein the failed connection is a connection that failed during run time, and further comprising:

rebooting the system; and

initializing the plurality of processors in accordance with the alternative path map.

7. The computer implemented method of claim 4 further comprising:

designating a system as unable to initialize only if an alternative path map cannot be generated due to insufficient functional interconnects remaining.

8. The computer implemented method of claim 1 wherein the step of identifying functional communication connections between each processor further comprises:

designating a processor in the plurality of processors as a master and designating all other processors in the plurality of processors as receiver processors;

initiating transmission of a data packet from a set of sending ports on the master to all receiver processors; and

opening a set of receiving ports on each receiver processor to determine whether each connection between the master and the receiver is a functional connection; and

identifying all functional connections in an output file.

9. The computer implemented method of claim 8 further comprising:

responsive to a determination that each processor in the plurality of processors has not been designated a master, iteratively designating a next processor as the master and designating all other processors as receiver processors; and

identifying all functional connections between the master and the receiver processors until each processor in the plurality of processors has been designated as the master.

10. The computer implemented method of claim 8 wherein the step of opening a set of receiver ports on each receiver processor further comprises:

opening a given receiver port in a set of receiver ports on the receiver processor;

determining whether the given receiver port receives the data packet sent by the master; and

responsive to determining that the given receiver port received the data packet, identifying a connection between the master and the given receiver port as a functional connection in the output file.

11. The computer implemented method of claim 10 further comprising:

responsive to a determination that each receiver port in the set of receiver ports has not been opened, iteratively opening each receiver port and determining if the opened receiver port received the data packet, wherein a connection between the master and the opened receiver port is identified as a functional connection in the output file if the opened receiver port received the data packet.

12. The computer implemented method of claim 1 wherein the interconnect matrix and path map are saved in non-volatile memory.

13. A computer program product comprising:

a computer usable medium having computer usable program code for symmetric multiprocessor interconnects, the computer program product comprising;

computer usable program code for identifying functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections;

computer usable program code for mapping every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections to form an interconnect matrix;

computer usable program code for creating a path map using the interconnect matrix, wherein the path map comprises a sequence of communication connections between the plurality of processors; and

computer usable program code for initializing the plurality of processors using the path map.

14. The computer program product of claim 13 further comprising:

computer usable program code for removing the failed connection from the interconnect matrix to form an updated interconnect matrix in response to a determination that a connection between two processors in the plurality of processors has failed.

15. The computer program product of claim 14 further comprising:

computer usable program code for generating an alternative path map based on the updated interconnect matrix in response to a determination that the failed connection is a connection in the path map, wherein the alternative path map bypasses the failed connection.

16. The computer program product of claim 13 wherein the failed connection is a connection that failed during initialization, and further comprising:

computer usable program code for continuing initialization of the plurality of processors in accordance with the alternative path map.

17. An apparatus for managing symmetric multiprocessor interconnects, the apparatus comprising:

a computing device, the computing device comprising;

a bus;

a storage device connected to the bus, wherein the storage device contains a computer usable program product; and

a plurality of processors, wherein at least one processor in the plurality of processors executes the computer usable program code to identify functional communication connections between each processor in a plurality of processors on a multiprocessor in an output file;

generate an interconnect matrix based on the output file, wherein an interconnect matrix is a map of every functional communication connection between any two processors in a plurality of processors;

create a path map based on the interconnect matrix, wherein a path map is a sequence of communication connections between a plurality of processors; and

initialize the plurality of processors in accordance with the path map.

18. The apparatus of claim 17 wherein the processor further executes the computer usable program code to remove the failed connection from the interconnect matrix in response to a determination that a connection between two processors in the plurality of processors has failed.

19. A multiprocessor, the multiprocessor comprising:

an interconnect bus;

a plurality of processors;

a memory; and

a controller, wherein the controller identifies functional communication connections between each processor in the plurality of processors in an output file in the memory;

generates an interconnect matrix based on the output file, wherein an interconnect matrix is a map of every functional communication connection between any two processors in a plurality of processors;

creates a path map based on the interconnect matrix, wherein a path map is a sequence of communication connections between a plurality of processors; and

initializes the plurality of processors in accordance with the path map.

20. The multiprocessor of claim 19 wherein the controller removes a failed connection from the interconnect matrix to form an updated interconnect matrix in response to a determination that a connection between two processors has failed, and wherein the controller generates an alternative path map based on the updated interconnect matrix in response to a determination that the failed connection is a connection in the path map, wherein the alternative path map bypasses the failed connection.