Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems

• US 20080168319A1
• Filed: 03/29/2007
• Published: 07/10/2008
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Si-Yung, Lee, Chang-Duck, Lee, Dong-Ryoul, Heo, Seok-won
• Granted Patent: US 7,904,790 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state

Abstract

An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.

Claims

1. An error correction code (ECC) controller for a flash memory device that stores M-bit data per memory cell, M being a positive integer equal to or greater than 2, the ECC controller comprising:

an encoder that is configured to generate first ECC data in response to input data that is to be stored in the flash memory device using a first error correction scheme and that is configured to generate second ECC data in response to the input data using a second error correction scheme; and

a decoder that is configured to calculate the number of errors in data read from the flash memory device and to correct the errors in the read data using one of the first ECC data or the second ECC data selectively according to the number of the errors.

2. The ECC controller of claim 1, wherein the encoder comprises:

a first encoder that is configured to generate the first ECC data using the first en-or correction scheme; and

a second encoder that is configured to generate the second ECC data using the second error correction scheme.

3. The ECC controller of claim 1, wherein the data read from the flash memory device comprises the read input data, the read first ECC data and the read second ECC data, and wherein the decoder comprises:

a first decoder that is configured to correct errors in the read data using the first ECC data contained in the read data;

a second decoder that is configured to correct errors in the read data using the second ECC data contained in the read data; and

a decoding controller that is configured to calculate the number of errors in the read data and that is further configured to control one of the first decoder or the second decoder to correct the errors in the read data selectively based on the number of errors.

4. The ECC controller of claim 3, wherein if the number of errors in the read data is 3 or less, the decoding controller controls the first decoder to correct the errors in the read data;

and if the number of errors in the read data is 4 or more, the decoding controller controls the second decoder to correct the errors in the read data.

5. The ECC controller of claim 1, wherein the first error correction scheme operates at a higher speed than the second error correction scheme, and wherein the second error correction scheme is capable of correcting a greater number of errors than the first error correction scheme.

6. The ECC controller of claim 1, wherein the first error correction scheme is an error correction scheme that uses a Bose-Chaudhuri-Hocquenghem (BCH) code, and the second error correction scheme is an error correction scheme that uses a Reed Solomon (RS) code.

7. The ECC controller of claim 1, wherein a memory cell array of the flash memory device includes a data area and a spare area, and wherein the input data is stored in the data area, and wherein the first ECC data and the second ECC data are stored in the spare area.

8. The ECC controller of claim 7, wherein each of the memory cells in the data area stores M-bit data, and wherein each of the memory cells in the spare area stores 1-bit data.

9. The ECC controller of claim 1, wherein the flash memory device is one of a NAND flash memory device, a NOR flash memory device, a phase change random access memory (PRAM) device or a magnetic random access memory (MRAM) device.

10. The ECC controller of claim 1, in combination with the flash memory device to form a memory system.

11. A method for correcting data errors, the method comprising:

receiving first data that is to be stored in a flash memory device;

generating first error correction code (ECC) data for the first data using a first error correction scheme;

generating second error correction code (ECC) data for the first data using a second error correction scheme;

storing the first data, the first ECC data, and the second ECC in the flash memory device;

reading the first data from the flash memory device;

determining the number of errors in the read first data; and

correcting the errors in the first data using one of the first ECC data or the second ECC data selectively based on -the determined number of the errors.

12. The method of claim 11, wherein storing the first data in the flash memory device comprises storing the first data in a plurality of memory cells of the flash memory device, where multiple bits of the first data are stored in at least some of the plurality of memory cells.

13. The method of claim 12, wherein correcting the errors in the first data comprises:

correcting the errors in the first data using the first ECC data if the number of errors in the read first data is 3 or less; and

correcting the errors in the first data using the second ECC data if the number of errors in the read first data is 4 or more.

14. The method of claim 12, wherein the first error correction scheme operates at a higher speed than the second error correction scheme, and wherein the second error correction scheme is capable of correcting a greater number of errors than the first error correction scheme.

15. The method of claim 12, wherein the first error correction scheme is an error correction scheme that uses a Bose-Chaudhuri-Hocquenghem (BCH) code, and wherein the second error correction scheme is an error correction scheme that uses a Reed Solomon (RS) code.

16. The method of claim 12, wherein a memory cell array of the flash memory device includes a data area and a spare area, wherein the first data is stored in the data area, and wherein the first ECC data and the second ECC data are stored in the spare area.

17. The method of claim 16, wherein each of the memory cells in the data area stores M-bit data, and each of the memory cells in the spare area stores 1 -bit data.

18. The method of claim 12, wherein the flash memory device is one of a NAND flash memory device, a NOR flash memory device, a phase change random access memory (PRAM) device or a magnetic random access memory (MRAM) device.

19. A method for correcting errors in data that is stored in a flash memory device, the method comprising:

reading the data along with first error correction code (ECC) data and second ECC data from the flash memory device;

determining a number of errors in the read data; and

selecting one of the first ECC data or the second ECC data for use in correcting the errors in the read data based on the determined number of the errors.

20. The method of claim 19, wherein the first ECC data is generated using a first error correction scheme and wherein the second ECC data is generated using a second error correction scheme.

21. The method of claim 19, wherein the first ECC data is selected for use in correcting the errors in the read data if the number of errors in the read data is 3 or less.

22. A memory system comprising:

a flash memory device that is configured to store M-bit data, M being a positive integer equal to or greater than 2; and

a memory controller that is configured to control the flash memory device, the memory controller comprising;

an encoder that is configured to generate first ECC data in response to input data that is to be stored in the flash memory device by using a first error correction scheme and that is configured to generate second ECC data in response to the input data by using a second error correction scheme, the input data, the first ECC data, and the second ECC data being stored in the flash memory device; and

a decoder that is configured to calculate the number of errors in data read from the flash memory device and to correct the errors in the read data using one of the first ECC data or the second ECC data selectively according to the number of errors.

23. The memory system of claim 22, wherein the encoder comprises:

a first encoder that is configured to generate the first ECC data in response to the input data by using the first error correction scheme; and

a second encoder that is configured to generate the second ECC data in response to the input data by using the second error correction scheme.

24. The memory system of claim 22, wherein the decoder comprises:

a first decoder that is configured to correct the errors in the read data using the first ECC data contained in the read data;

a second decoder that is configured to correct the errors in the read data using the second ECC data contained in the read data; and

a decoding controller that is configured to calculate the number of errors in the read data and that is further configured to control one of the first decoder or the second decoder to correct the errors in the read data selectively according to the number of errors.

25. The memory system of claim 22, wherein the first error correction scheme is a high-speed error correction scheme that supports an on-the-fly function, and the second error correction scheme is a high-performance error correction scheme that does not support the on-the-fly function.

26. The memory system of claim 22, wherein the first error correction scheme is an error correction scheme that uses a Bose-Chaudhuri-Hocquenghem (BCH) code, and the second error correction scheme is an error correction scheme that uses a Reed Solomon (RS) code.

27. The memory system of claim 22, wherein a memory cell array of the flash memory device includes a data area and a spare area, and wherein the input data is stored in the data area, and wherein the first ECC data and the second ECC data are stored in the spare area.

28. The memory system of claim 27, wherein each of memory cells in the data area stores M-bit data, and wherein each of memory cells in the spare area stores 1-bit data.