Properties In Electronic Design Automation

• US 20080168410A1
• Filed: 10/09/2007
• Published: 07/10/2008
• Est. Priority Date: 10/09/2006
• Status: Abandoned Application

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Cohen, Ellis, Pikus, Fedor G.
• Application Number:
  US11/869,717
• Publication Number:
  US 20080168410A1
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property'"'"'s value is not dependent upon the value of any other properties. Alternately, a property may be a compound property, where the definition of the property'"'"'s value incorporates another, previously-determined property value. Still further, a property may be an alternative property, where the property is assigned one value definition under a first set of conditions and assigned another value definition under a second set of conditions. A first electronic design automation process may generate one or more property values. The generated property values then can be passed to another electronic design automation process in the design analysis flow for its use.

Claims

1. A method of analyzing a circuit design, comprising:

receiving a circuit design into an electronic design automation process;

executing the electronic design automation process using the circuit design;

during the execution of the electronic design automation process, determining a value for a property, the property

being associated with a first design object in the circuit design,

having a user-specified value definition, and

having a value derived from a feature of at least one second design object different from the first design object; and

storing the property value in a memory storage medium.

2. The method recited in claim 1, wherein the first design object is selected from the group consisting of:

a polygon edge, one or more vertices of a polygon, a collection of geometric elements in a layout circuit design, a placement of a hierarchical cell in a layout circuit design, and an item in a logical circuit design.

3. The method recited in claim 2, wherein the first design object is a collection of geometric elements in a layout design selected from the group consisting of:

a group of polygon edges, a group of polygons, a net, a hierarchical cell in the layout design, every hierarchical cell of a specified type in the layout design, and a collection of all of the geometric elements in a layer of the layout design.

4. The method recited in claim 2, wherein the first design object is an item in a logical circuit design selected from the group consisting of:

a net, a device, and an instance pin.

5. The method recited in claim 1, wherein the second design object is selected from the group consisting of:

a polygon edge, one or more vertices of a polygon, a polygon, a collection of geometric elements in a layout circuit design, a placement of a hierarchical cell in a layout circuit design, and an item in a logical circuit design.

6. The method recited in claim 5, wherein the second design object is a collection of geometric elements in a layout design selected from the group consisting of:

a group of polygon edges, a group of polygons, a net, a hierarchical cell in the layout design, every hierarchical cell of a specified type in the layout design, and a collection of all of the geometric elements in a layer of the layout design.

7. The method recited in claim 5, wherein the second design object is an item in a logical circuit design selected from the group consisting of:

a net, a device, and an instance pin.

8. The method recited in claim 1, wherein the feature is a characteristic of the at least one second design object.

9. The method recited in claim 1, wherein the feature is a value of a second property associated with the at least one second design object.

10. The method recited in claim 1, wherein the at least one second design object is selected from the group consisting of:

geometric elements that touch the design object with which the property is associated, geometric elements that intersect the design object with which the property is associated, geometric elements that are within a specified proximity of the design object with which the property is associated, geometric elements that are within a specified proximity of the design object with which the property is associated or are within a specified proximity of another related design object, geometric elements that overlap the design object with which the property is associated, portions of geometric elements that are clipped by the design object with which the property is associated, items in a logical circuit design that belong a same device as the design object, items in a logical circuit design that share a net with the design object; and

items in a logical circuit design that share a reference identifier with the design object.

11. The method recited in claim 1, wherein the property has a value definition that includes a variable function.

12. The method recited in claim 11, wherein the variable function is described in a program script.

13. The method recited in claim 1, wherein the property has alternate value definitions to determine a first value under a first set of conditions, and a second value under a second set of conditions different from the first set of conditions, such that at least one of the first value and the second value is derived from the feature of the at least one second design object.

14. The method recited in claim 1, wherein the property has two or more concurrent value definitions, such that at such that at least one of the value definitions employs the feature of the at least one second design object.

17. The method recited in claim 1, further comprising

during the execution of the electronic design automation process, adding at least one value definition for the property, the value definition employing the feature of the at least one second design object;

and

determining a value for each value definition of the property.

18. The method recited in claim 1, wherein the feature is a characteristic of the at least one second design object.

19. The method recited in claim 18, wherein the feature is a value of a second property associated with the at least one second design object.

15. The method recited in 14, wherein the feature is a characteristic of the at least one second design object.

16. The method recited in 14, wherein the feature is a value of a second property associated with the at least one second design object.

20. A method of analyzing a circuit design, comprising:

receiving a circuit design into an electronic design automation process;

executing the electronic design automation process using the circuit design;

during the execution of the electronic design automation process, determining a value for a property, the property

being associated with a first design object in the circuit design,

having a user-specified value definition, and

having a value derived from geometric elements separate from the design object with which the property is associated.