MULTI-CORE PROCESSOR

• US 20080168466A1
• Filed: 03/17/2008
• Published: 07/10/2008
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kobayashi, Kazunari, Nitta, Daisuke, Kumagai, Tomonori
• Granted Patent: US 8,516,491 B2
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 2209/5017 Task decomposition
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

An algorithm in a multi-core processor having a plurality of cores for deciding processing allocation to each core to distribute the processing load thereof, and an efficient processing allocation algorithm simplified for software engineers are established. In order to achieve the above processing load distribution, the multi-core processor includes a plurality of basic modules divided into minimum configuration units, each having a uniform input/output format interface, so as to perform required processing contents in the overall processor. As an initial allocation, the above plurality of basic modules are allocated in distribution to the above plurality of cores, and subsequently, based on functional information of each core, the above plurality of initially allocated basic modules are relocated either periodically or at appropriate timing.

Claims

1. A processing load distribution method in a multi-core processor having a plurality of cores, comprising:

forming a plurality of basic modules, including processing contents required for the overall processor being divided into minimum configuration units each having a unified input/output format interface;

as initial allocation, allocating in distribution the plurality of basic modules to the plurality of cores; and

subsequently, based on functional information of the each core, relocating the plurality of initially allocated basic modules either periodically or at appropriate timing.

2. The processing load distribution method in the multi-core processor according to claim 1,

wherein the functional information of each core is information obtained from at least one of the functions of:

i) counting the number of signals requested to the self-core and the number of signals being output from the self-core to other cores;

ii) measuring a reception buffer storage capacity and a transmission buffer storage capacity incorporated in the self-core; and

iii) measuring the number of queues requested to the self-core and the number of queues requested to other cores.

3. The processing load distribution method in the multi-core processor according to claim 1,

wherein, the plurality of basic modules are relocated in a manner such that a processing capacity of each core comes to have a maximum value for each of the plurality of basic modules, using the entire plurality of cores.

4. The processing load distribution method in the multi-core processor according to claim 1,

wherein the plurality of basic modules are relocated by means that, among the plurality of cores, a core having a high use priority undertakes a basic module in a core having a low use priority.

5. The processing load distribution method in the multi-core processor according to claim 1,

wherein, by leaving at least one core among the plurality of cores, the plurality of basic modules are relocated to other cores in a manner such that a processing capacity of each core comes to have a maximum value for each of the plurality of basic modules.

6. A multi-core processor having a plurality of cores, comprising:

a core section having the plurality of cores; and

a processor section,

the processor section further comprising;

a reception section transferring a processing object data received from the outside to each core in the core section;

a transmission section transmitting a data being output to the outside, from the core section to the outside;

a basic module transmission section deciding to which of the plurality of cores the basic module transmitted from the outside is to be allocated, and performing relocation processing of the basic module to the object core; and

a basic module allocation control section informing the entire plurality of cores about a relocation control method specified from the outside,

wherein, as initial allocation, the plurality of basic modules are allocated in distribution to the plurality of cores, and

wherein, based on the functional information of each core, the plurality of initially allocated basic modules are relocated either periodically or at appropriate timing.

7. The multi-core processor according to claim 6,

wherein the functional information of each core is information obtained from at least one of the functions of:

i) counting the number of signals requested to the self-core and the number of signals being output from the self-core to other cores;

ii) measuring a reception buffer storage capacity and a transmission buffer storage capacity incorporated in the self-core; and

iii) measuring the number of queues requested to the self-core and the number of queues requested to other cores.

8. The multi-core processor according to claim 6,

wherein, the plurality of basic modules are relocated so that a processing capacity of each core comes to have a maximum value for each of the plurality of basic modules, using the entire plurality of cores.

9. The multi-core processor according to claim 6,

wherein, among the plurality of cores, a core having a high use priority undertakes a basic module in a core of low use priority, so that the plurality of basic modules are relocated.

10. The multi-core processor according to claim 6,

wherein, among the plurality of cores, at least one core is left, and the plurality of basic modules are relocated to other cores so that a processing capacity of each core comes to have a maximum value for each of the plurality of basic modules.

11. The multi-core processor according to claim 6,

wherein each of the plurality of cores in the core section comprises:

a data input/output section;

a buffer measurement section measuring an input buffer amount and an output buffer amount in the data input/output section;

a program execution area having the basic modules allocated therein; and

a core use rate measurement section measuring a use rate of the overall program execution area and a use rate per basic module, and

each of the plurality of cores further comprises;

a core state transmission section outputting a core state based on the input buffer amount and the output buffer amount, measured by the buffer measurement section, and the program execution area use rate, measured by the core use rate measurement section;

an information database describing state information of other cores obtained through a communication section; and

a module allocation control section comparing the self-core state, transmitted from the core state transmission section, with a state of another core described in the information database, taking charge of execution of processes before and after the basic module allocated in the self-core, and performing relocation control of the basic modules when a difference exists between the overall core use rates.