Semiconductor device

• US 20080169467A1
• Filed: 01/08/2008
• Published: 07/17/2008
• Est. Priority Date: 01/12/2007
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nagamine, Hisayuki, Yamagami, Minoru
• Granted Patent: US 8,704,223 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.

Claims

1. A semiconductor device having a characteristic checking element disposed in a dicing line and an internal measurement pad disposed in the semiconductor device and connected to the characteristic checking element, wherein:

the internal measurement pad is applied with an electric voltage during a semiconductor device operation test executed in a wafer state so that a function of the characteristic checking element is destroyed.

2. The semiconductor device as claimed in claim 1, wherein the internal measurement pad and the characteristic checking element are connected by a connection wiring which is disposed across a part of a sub-connection wiring formed at the periphery of the semiconductor device after the part of the sub-connection wiring is cut.

3. The semiconductor device as claimed in claim 2, wherein a plurality of internal measurement pads are disposed in a wafer in correspondence to a plurality of semiconductor devices formed on the wafer, the internal measurement pads being connected in common in the dicing lines.

4. The semiconductor device as claimed in claim 1, wherein the characteristic checking element is a checking transistor having a drain and a source connected to corresponding measurement pads, respectively, and a gate connected to a corresponding measurement pad and to the internal measurement pad, the internal measurement pad being applied with an electric voltage during the semiconductor device operation test so that the gate of the checking transistor is broken.

5. The semiconductor device as claimed in claim 1, wherein the characteristic checking element comprises a plurality of checking transistors having drains connected to individual measurement pads, respectively, sources connected to a common measurement pad, and gates connected to a common measurement pad and to the internal measurement pad, the internal measurement pad being applied with an electric voltage during the semiconductor device operation test so that the gates of the checking transistors are broken.

6. The semiconductor device as claimed in claim 1, wherein the characteristic checking element is a checking resistance element having measurement pads formed on both ends thereof, the checking resistance element being provided with a transistor having a gate connected to a part of the checking resistance element and to the internal measurement pad and a drain and a source which are connected to a substrate electric potential, the internal measurement pad being applied with an electric voltage during the semiconductor device operation test so that the gate of the transistor is broken.

7. The semiconductor device as claimed in claim 6, wherein the transistor is disposed in the dicing line, the gate of the transistor and the part of the checking resistance element being connected through a connection wiring which is a conductive wiring layer forming the checking resistance element or a lower conductive wiring layer.

8. The semiconductor device as claimed in claim 1, wherein the characteristic checking element is a checking resistance element having measurement pads formed on both ends thereof, the checking resistance element being provided with a transistor having a gate connected to the internal measurement pad, one diffusion layer connected to a part of the checking resistance element, and the other diffusion layer connected to a substrate electric potential, the internal measurement pad being applied with an electric voltage during the semiconductor device operation test so that the gate of the transistor is broken.

9. The semiconductor device as claimed in claim 8, wherein the transistor is disposed in the dicing line, the one diffusion layer of the transistor and the part of the checking resistance element being connected through a connection wiring which is a conductive wiring layer forming the checking resistance element or a lower conductive wiring layer.