Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

• US 20080169512A1
• Filed: 12/20/2007
• Published: 07/17/2008
• Est. Priority Date: 08/10/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Been-Yih Jin, Brian S. Doyle, Nancy M. Zelick, Robert Chau, Suman Datta
• Inventors: Zelick, Nancy M., Jin, Been-Yih, Doyle, Brian S., Datta, Suman, Chau, Robert
• Granted Patent: US 7,960,794 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si_1-x Ge_x layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si_1-x Ge_x layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si_1-y Ge_y layer, having the Ge content y higher than the Ge content x in the relaxed Si_1-x Ge_x layer, is epitaxially grown on the fin. The Si_1-y Ge_y layer covers the top and two sidewalls of the fin. The compressive stress in the Si_1-y Ge_y layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

Claims

1. A semiconductor transistor, comprising:

an insulating layer;

a fin, having opposing sidewalls and a top surface, the fin of a first material having a first lattice spacing, above the insulating layer;

a layer of a second material covering the fin, the layer of the second material having a second lattice spacing substantially larger than the first lattice spacing of the first material;

a dielectric layer, formed on the layer of the second material; and

a gate electrode with the dielectric layer between the gate electrode and the opposing sidewalls and the top surface of the fin.

2. The semiconductor transistor of claim 1, wherein the first material has a germanium content of at least 15% less than the second material.

3. The semiconductor transistor of claim 1, wherein the first material has a germanium content of about 15% and the second material has a germanium content of about 30%.

4. The semiconductor transistor of claim 1, wherein the layer of the second material covers the top surface and the opposing sidewalls of the fin.

5. The semiconductor transistor of claim 4, wherein the layer of the second material covering the top surface and the opposing sidewalls of the fin is under a compressive stress.

6. The semiconductor transistor of claim 5, wherein the compressive stress in the layer of the second material grown on the fin increases mobility of holes in the channel of a p-MOS structure.

7-11. -11. (canceled)

12. A semiconductor transistor structure, comprising:

an insulating layer;

a first fin on the insulating layer;

a second fin on the insulating layer, wherein the first fin and the second fin are formed from a first material having a first lattice spacing;

a second layer of a second material formed on a first fin, wherein the second layer of the second material has a second lattice spacing substantially larger than the first lattice spacing; and

a third layer of a third material formed on a second fin, wherein the third material has a third lattice spacing substantially smaller than the first lattice spacing.

13. The semiconductor transistor structure of claim 12, wherein the second material comprises silicon germanium and the third material comprises silicon.

14. The semiconductor transistor structure of claim 12 further comprising:

a first gate dielectric on the second layer;

a second gate dielectric on the third layer;

a first gate electrode on the first gate dielectric;

a second gate electrode on the second gate dielectric;

a first source region and a first drain region at opposing sides of the first gate electrode; and

a second source region and a second drain region at opposing sides of the second gate electrode.

15. The semiconductor transistor structure of claim 12, wherein the second layer covers a top surface and two opposing sidewalls of the first fin and the third layer covers the top and two sidewalls of the second fin.

16-20. -20. (canceled)