Analog-to-Digital Converter with DC Balanced Serialized Output

• US 20080169947A1
• Filed: 01/11/2008
• Published: 07/17/2008
• Est. Priority Date: 01/11/2007
• Status: Abandoned Application

• Current Assignee: Slicex Incorporated
• Original Assignee: Slicex Incorporated
• Inventors: Harper, Marcellus C.
• Application Number:
  US12/013,039
• Publication Number:
  US 20080169947A1
• Time in Patent Office: Days
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A method of serializing parallel output from an analog-to-digital converter includes receiving a parallel output from an analog-to-digital converter; serializing the parallel output; and encoding the serialized output such that it is DC balanced. A system for serializing and DC balancing an analog-to-digital converter output includes an analog-to-digital converter that outputs digital data over a parallel bus; a serializer configured to receive said digital data from said parallel bus, said serializer serializing said digital data into serial output; and a means for encoding the serial output such that it is DC balanced.

Claims

1. A method of serializing parallel output from an analog-to-digital converter comprising:

receiving a parallel output from an analog-to-digital converter;

serializing said parallel output; and

encoding said serialized output such that a data stream carrying said serialized output is DC balanced.

2. The method of claim 1, further comprising isolating said digital-to-analog converter from low-frequency or DC voltages.

3. The method of claim 2, wherein said isolation is accomplished by interposing a capacitor in an output line carrying a portion of said data stream.

4. The method of claim 3, wherein said encoding said serialized output further comprises encoding said serialized output using an 8 B/10 B protocol.

5. The method of claim 2, further comprising transmitting framing or timing information in at least one separate data pipe.

6. The method of claim 5, wherein a plurality of serialized data streams utilizes the same framing or timing information.

7. The method of claim 6, wherein said framing or timing information comprises a master clock signal, an 8 B/10 B timing signal, and a framing signal.

8. The method of claim 1, wherein said serialized output is DC balanced by encoding said data stream with a substantially similar number of digital ones and zeros.

9. A system for serializing and DC balancing an analog-to-digital converter output comprising:

an analog-to-digital converter, said analog-to-digital converter receiving an analog signal and outputting corresponding digital data on a parallel bus, wherein said analog-to-digital converter is at least partially isolated from low-frequency or DC voltages on an output line;

a serializer configured to receive said digital data from said parallel bus, said serializer serializing said digital data into serial output;

a means for encoding said serial output such that said serial output is DC balanced.

10. The system of claim 9, wherein said analog-to-digital converter is at least partially isolated from low-frequency or DC voltages on said output line by placing a capacitance in said output line.

11. The system of claim 9, wherein said means for encoding comprises a separate chip, said separate chip receiving said serial output;

said separate chip encoding said serial output such that said serial output is DC balanced.

12. The system of claim 9, wherein said means for encoding comprises circuitry internal to said serializer.

13. The system of claim 9, wherein said means for encoding comprises an 8 B/10 B encoder.

14. The system of claim 9, wherein said serial output further comprises a separate data stream containing timing or framing information.

15. The system of claim 9, wherein said serialized output is transmitted over low voltage differential pairs.

16. The system of claim 9, wherein said analog-to-digital converter, said serializer, and said encoder are contained within a load board, typical of those found in Automated Test Equipment (ATE) applications.

17. The system of claim 9, wherein said means for encoding is further configured to create a DC balanced output on each signal path that carries a portion of said serial output.

18. The system of claim 9, wherein said analog-to-digital converter, said serializer, and said encoder are contained within a single integrated circuit.