DISPLAY DEVICE

• US 20080170028A1
• Filed: 01/10/2008
• Published: 07/17/2008
• Est. Priority Date: 01/12/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YOSHIDA, Yasunori
• Granted Patent: US 8,643,583 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 2310/024 Scrolling of light from the illumination source over the display in combination with the scanning of the display screen
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/16 Determination of a pixel data signal depending on the signal applied in the previous frame
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/342 using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

To provide an active matrix display device in which power consumption of a signal line driver circuit can be suppressed, so that power consumption of the entire memory can be suppressed. A plurality of memory circuits which can write data of a video signal input to a pixel in one line period and can hold the data are provided in a signal line driver circuit of a display device. Then, the data held in each memory circuit is input to a pixel of a corresponding line as a video signal. By providing two or more memory circuits in a driver circuit, pieces of data of video signals corresponding to two or more line periods can be concurrently held in the memory circuits.

Claims

1. A display device comprising:

a pixel portion including a plurality of pixels; and

a signal line driver circuit,

wherein the signal line driver circuit includes a first memory circuit which can hold pieces of data of the video signals corresponding to a plurality of line periods which appear discontinuously.

2. A display device according to claim 1, further comprising a scan line driver circuit selecting the plurality of pixels in each line.

3. A display device according to claim 1, further comprising a sampling circuit for sampling video signals,

wherein the memory circuit stores the sampled video signals and inputs the sampled video signals to the plurality of pixels.

4. A display device according to claim 1, wherein the first memory circuit is a latch circuit.

5. A display device according to claim 1, wherein the signal line driver circuit further includes a D/A converter circuit converting the video signals output from the plurality of memory circuits into analog video signals.

6. A display device according to claim 1, further comprising:

at least one second memory circuit for storing the pieces of data of the video signals corresponding to the plurality of line periods; and

a data comparison circuit configured to read the pieces of data of the video signals from the at least one second memory circuits, compare the pieces of the data, and extract a group including a plurality of line periods among which pieces of data of video signals correspond to each other.

7. A display device according to claim 6, wherein the data comparison circuit is configured to control the first memory circuit so that writing of the video signals corresponding to each other is performed only once during the plurality of line periods.

8. A display device comprising:

at least one first memory circuit configured to store pieces of data of video signals corresponding to a plurality of line periods;

a data comparison circuit configured to read the pieces of data of the video signals from the at least one first memory circuit, compare the pieces of data, and extract a plurality of groups each including a plurality of line periods in which pieces of data of video signals correspond to each other;

a pixel portion including a plurality of pixels; and

a signal line driver circuit including a plurality of second memory circuits.

9. A display device according to claim 8, wherein the plurality of second memory circuits are latch circuits.

10. A display device according to claim 8, wherein the data comparison portion includes:

a counter configured to count a number of the plurality of line periods included in each of the plurality of groups; and

an arithmetic circuit selecting at least one of the plurality of groups in accordance with the number of the plurality of line periods.

11. A display device according to claim 10, wherein the data comparison circuit is configured to control the plurality of memory circuits so that writing of the video signals is performed only once during the plurality of line periods included in each of the selected at least one group among the plurality of groups.