METHODS AND APPARATUS OF STACKING DRAMS
First Claim
Patent Images
1. A memory device for electrical connection to a memory bus, the memory device comprising:
- a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and
an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a second speed;
wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.
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Abstract
Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
217 Citations
25 Claims
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1. A memory device for electrical connection to a memory bus, the memory device comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; andan interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a second speed; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A memory device for use with a memory bus, the memory bus comprising:
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a plurality of dynamic random access memory (“
DRAM”
) integrated circuits each comprising a memory core of a plurality of cells accessible at low speed; andan interface integrated circuit for providing an interface, at a high speed relative to the low speed between the DRAM integrated circuits and the memory bus; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.
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25. A memory device for use with a memory bus, the memory bus comprising:
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means for stacking a plurality of dynamic random access memory (“
DRAM”
) integrated circuits each comprising a memory core of a plurality of cells accessible at a first speed; andmeans for providing an interface between the DRAM integrated circuits and the memory bus at a second speed; wherein the means for providing the interface is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the means for providing the interface is electrically coupled.
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Specification